Build starting @ 2019-03-05T01:52:31.305763 Running make -C /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid run (with MAKEFLAGS=' -j --jobserver-fds=3,4') --------------------------------------------------------------------------- make[1]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make clean make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' rm -rf build run.ok cd clb && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' cd clb_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' cd iob && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' cd iob_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' cd mmcm && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' cd pll && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' cd ps7_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' cd bram && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' cd bram_block && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' cd bram_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' cd dsp && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' cd dsp_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' cd fifo_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' cd monitor && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' cd monitor_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' cd cfg_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' cd orphan_int_column && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' cd clk_hrow && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' cd clk_bufg && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make database make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' bash generate.sh build/tiles tiles ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate_tiles.tcl # source "$::env(FUZDIR)/util.tcl" ## proc min_ysite { duts_in_column } { ## # Given a list of sites, return the one with the lowest Y coordinate ## ## set min_dut_y 9999999 ## ## foreach dut $duts_in_column { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## if { $dut_y < $min_dut_y } { ## set selected_dut $dut ## set min_dut_y $dut_y ## } ## } ## return $selected_dut ## } ## proc group_dut_cols { duts ypitch } { ## # Group a list of sites into pitch sized buckets ## # Ex: IOBs occur 75 to a CMT column ## # Set pitch to 75 to get 0-74 in one bucket, 75-149 in a second, etc ## # X0Y0 {IOB_X0Y49 IOB_X0Y48 IOB_X0Y47 ... } ## # Anything with a different x is automatically in a different bucket ## ## # LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column) ## set dut_columns "" ## foreach dut $duts { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## # 75 per column => 0, 75, 150, etc ## set y_column [expr ($dut_y / $ypitch) * $ypitch] ## dict append dut_columns "X${dut_x}Y${y_column}" "$dut " ## } ## return $dut_columns ## } ## proc loc_dut_col_bels { dut_columns cellpre cellpost } { ## # set cellpre di ## ## # Pick the smallest Y in each column and LOC a cell to it ## # cells must be named like $cellpre[$dut_index] ## # Return the selected sites ## ## set ret_bels {} ## set dut_index 0 ## ## dict for {column duts_in_column} $dut_columns { ## set sel_bel_str [min_ysite $duts_in_column] ## set sel_bel [get_bels $sel_bel_str] ## if {"$sel_bel" == ""} {error "Bad bel $sel_bel from bel str $sel_bel_str"} ## set sel_site [get_sites -of_objects $sel_bel] ## if {"$sel_site" == ""} {error "Bad site $sel_site from bel $sel_bel"} ## ## set cell [get_cells $cellpre$dut_index$cellpost] ## puts "LOCing cell $cell to site $sel_site (from bel $sel_bel)" ## set_property LOC $sel_site $cell ## ## set dut_index [expr $dut_index + 1] ## lappend ret_bels $sel_bel ## } ## ## return $ret_bels ## } ## proc loc_dut_col_sites { dut_columns cellpre cellpost } { ## set bels [loc_dut_col_bels $dut_columns $cellpre $cellpost] ## set sites [get_sites -of_objects $bels] ## return $sites ## } ## proc make_io_pad_sites {} { ## # get all possible IOB pins ## foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { ## set site [get_sites -of_objects $pad] ## if {[llength $site] == 0} { ## continue ## } ## if [string match IOB33* [get_property SITE_TYPE $site]] { ## dict append io_pad_sites $site $pad ## } ## } ## return $io_pad_sites ## } ## proc make_iob_pads {} { ## set io_pad_sites [make_io_pad_sites] ## ## set iopad "" ## dict for {key value} $io_pad_sites { ## # Some sites have more than one pad? ## lappend iopad [lindex $value 0] ## } ## return $iopad ## } ## proc make_iob_sites {} { ## set io_pad_sites [make_io_pad_sites] ## ## set sites "" ## dict for {key value} $io_pad_sites { ## lappend sites $key ## } ## return $sites ## } ## proc assign_iobs_old {} { ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] ## } ## proc assign_iobs {} { ## # Set all I/Os on the bus to valid values somewhere on the chip ## # The iob fuzzer sets these to more specific values ## ## # All possible IOs ## set iopad [make_iob_pads] ## # Basic pins ## # XXX: not all pads are valid, but seems to be working for now ## # Maybe better to set to XRAY_PIN_* and take out of the list? ## set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb] ## ## # din bus ## set fixed_pins 3 ## set iports [get_ports di*] ## for {set i 0} {$i < [llength $iports]} {incr i} { ## set pad [lindex $iopad [expr $i+$fixed_pins]] ## set port [lindex $iports $i] ## set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port ## } ## } ## proc make_project {} { ## # Generate .bit only over ROI ## make_project_roi XRAY_ROI_TILEGRID ## } ## proc make_project_roi { roi_var } { ## # 6 CMTs in our reference part ## # What is the largest? ## set n_di 16 ## ## create_project -force -part $::env(XRAY_PART) design design ## ## read_verilog "$::env(FUZDIR)/top.v" ## synth_design -top top -verilog_define N_DI=$n_di ## ## assign_iobs ## ## create_pblock roi ## add_cells_to_pblock [get_pblocks roi] [get_cells roi] ## foreach roi "$::env($roi_var)" { ## puts "ROI: $roi" ## resize_pblock [get_pblocks roi] -add "$roi" ## } ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## set_param tcl.collectionResultDisplayLimit 0 ## ## set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## } # proc write_tiles_txt {} { # # Get all tiles, ie not just the selected LUTs # set tiles [get_tiles] # # # Write tiles.txt with site metadata # set fp [open "tiles.txt" w] # foreach tile $tiles { # set type [get_property TYPE $tile] # set grid_x [get_property GRID_POINT_X $tile] # set grid_y [get_property GRID_POINT_Y $tile] # set sites [get_sites -quiet -of_objects $tile] # set typed_sites {} # # if [llength $sites] { # set site_types [get_property SITE_TYPE $sites] # foreach t $site_types s $sites { # lappend typed_sites $t $s # } # } # # puts $fp "$type $tile $grid_x $grid_y $typed_sites" # } # close $fp # } # proc run {} { # # Generate grid of entire part # make_project_roi XRAY_ROI_TILEGRID # # place_design # route_design # write_checkpoint -force design.dcp # write_bitstream -force design.bit # # write_tiles_txt # } # run Command: synth_design -top top -verilog_define N_DI=16 Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29915 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 26935 ; free virtual = 55111 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] Parameter DIN_N bound to: 16 - type: integer Parameter DOUT_N bound to: 108 - type: integer INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] INFO: [Synth 8-638] synthesizing module 'roi' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized0' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized1' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized2' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized3' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized4' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized5' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized7' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized7' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized8' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized9' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized9' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized10' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized10' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized11' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized11' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized12' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized12' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized13' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized13' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized14' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized14' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized15' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized15' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized16' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized16' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized17' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized17' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized18' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized18' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized19' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized19' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized20' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized20' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized21' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized21' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized22' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized22' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized23' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized23' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized24' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized24' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized25' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized25' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized26' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized26' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized27' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized27' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized28' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized28' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized29' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized29' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized30' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized30' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized31' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized31' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized32' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized32' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized33' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized33' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized34' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized34' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized35' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized35' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized36' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized36' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized37' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized37' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized38' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized38' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized39' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized39' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized40' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized40' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized41' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized41' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized42' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized42' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized43' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized43' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized44' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized44' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized45' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized45' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized46' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized46' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized47' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized47' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized48' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized48' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized49' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized49' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized50' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized50' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized51' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized51' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized52' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized52' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized53' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized53' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized54' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized54' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized55' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized55' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized56' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized56' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized57' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized57' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized58' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized58' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized59' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized59' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized60' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized60' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized61' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized61' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized62' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized62' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized63' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized63' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized64' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized64' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized65' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized65' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized66' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized66' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized67' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized67' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized68' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized68' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized69' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized69' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized70' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized70' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized71' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized71' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized72' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized72' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized73' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized73' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized74' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized74' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized75' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized75' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized76' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized76' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized77' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized77' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized78' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized78' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized79' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized79' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized80' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized80' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized81' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized81' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized82' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized82' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized83' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized83' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized84' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized84' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized85' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized85' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized86' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized86' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized87' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized87' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized88' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized88' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized89' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized89' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized90' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized90' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized91' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized91' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized92' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized92' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized93' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized93' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized94' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized94' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized95' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized95' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized96' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized96' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized97' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized97' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized98' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized98' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'RAMB36E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized0' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized3' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized4' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized5' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized6' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-256] done synthesizing module 'roi' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-256] done synthesizing module 'top' (5#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] WARNING: [Synth 8-3331] design roi has unconnected port clk --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 26939 ; free virtual = 55118 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 26940 ; free virtual = 55118 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 26939 ; free virtual = 55118 --------------------------------------------------------------------------------- WARNING: [Synth 8-3936] Found unconnected internal register 'din_reg' and it is trimmed from '16' to '8' bits. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:36] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1205.949 ; gain = 110.508 ; free physical = 26931 ; free virtual = 55110 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (di_bufs[8].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[9].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[10].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[11].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[12].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[13].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[14].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[14]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[13]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[12]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[11]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[10]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[9]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[8]) is unused and will be removed from module top. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1328.918 ; gain = 233.477 ; free physical = 26788 ; free virtual = 54970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1328.918 ; gain = 233.477 ; free physical = 26786 ; free virtual = 54969 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54967 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54968 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54968 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 3| |2 |LUT3 | 108| |3 |LUT6 | 100| |4 |RAMB36E1 | 8| |5 |FDRE | 125| |6 |IBUF | 11| |7 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 356| |2 | roi |roi | 216| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26785 ; free virtual = 54967 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 96 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 26786 ; free virtual = 54969 Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.941 ; gain = 243.492 ; free physical = 26787 ; free virtual = 54970 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 230 Infos, 96 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1472.961 ; gain = 390.074 ; free physical = 26683 ; free virtual = 54868 ROI: SLICE_X0Y0:SLICE_X43Y99 ROI: RAMB18_X0Y0:RAMB18_X2Y39 ROI: RAMB36_X0Y0:RAMB36_X2Y19 ROI: DSP48_X0Y0:DSP48_X1Y39 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1536.992 ; gain = 0.000 ; free physical = 26677 ; free virtual = 54862 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17075422c Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1536.992 ; gain = 0.000 ; free physical = 26677 ; free virtual = 54862 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1922.480 ; gain = 0.000 ; free physical = 26328 ; free virtual = 54520 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 196761f3e Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 26319 ; free virtual = 54511 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 26319 ; free virtual = 54511 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 26319 ; free virtual = 54511 Phase 1 Placer Initialization | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 26319 ; free virtual = 54511 Phase 2 Global Placement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26301 ; free virtual = 54493 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26301 ; free virtual = 54493 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18f2ccf33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26301 ; free virtual = 54493 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26301 ; free virtual = 54493 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26301 ; free virtual = 54493 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26297 ; free virtual = 54489 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26297 ; free virtual = 54489 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26297 ; free virtual = 54489 Phase 3 Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26297 ; free virtual = 54489 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26297 ; free virtual = 54489 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26299 ; free virtual = 54491 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26299 ; free virtual = 54491 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1ce33f28d Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26299 ; free virtual = 54491 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ce33f28d Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26299 ; free virtual = 54491 Ending Placer Task | Checksum: 14c774d33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 26311 ; free virtual = 54504 240 Infos, 98 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 2042.539 ; gain = 569.578 ; free physical = 26311 ; free virtual = 54504 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9c4f4a11 ConstDB: 0 ShapeSum: b0280322 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2072.184 ; gain = 29.645 ; free physical = 26093 ; free virtual = 54293 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2078.172 ; gain = 35.633 ; free physical = 26061 ; free virtual = 54261 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2078.172 ; gain = 35.633 ; free physical = 26061 ; free virtual = 54261 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b8accb7e Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26048 ; free virtual = 54248 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: fc55de3b Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26052 ; free virtual = 54252 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26050 ; free virtual = 54250 Phase 4 Rip-up And Reroute | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26050 ; free virtual = 54250 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26050 ; free virtual = 54250 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26050 ; free virtual = 54250 Phase 6 Post Hold Fix | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26050 ; free virtual = 54250 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0324117 % Global Horizontal Routing Utilization = 0.0410751 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. Phase 7 Route finalize | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26050 ; free virtual = 54250 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26049 ; free virtual = 54249 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26049 ; free virtual = 54249 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.227 ; gain = 50.688 ; free physical = 26082 ; free virtual = 54282 Routing Is Done. 247 Infos, 99 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2132.016 ; gain = 89.477 ; free physical = 26082 ; free virtual = 54282 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2132.016 ; gain = 0.000 ; free physical = 26081 ; free virtual = 54283 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:53:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 257 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2473.121 ; gain = 341.105 ; free physical = 26035 ; free virtual = 54248 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:53:51 2019... mkdir -p build/basicdb cd build && python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate.py \ --tiles /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/tiles.txt \ --out /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/basicdb/tilegrid.json cd iob && make cd iob_int && make cd monitor && make cd bram && make cd bram_block && make cd bram_int && make cd clb && make cd clb_int && make cd dsp && make cd fifo_int && make cd cfg_int && make cd monitor_int && make make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 1 --design params.csv --dframe 26 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 14 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # gets $fp line # # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 2] # set pin_str [lindex $line 3] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } # run ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } # generate_top ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 3] # set pin_str [lindex $line 4] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32432 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32433 INFO: Helper process launched with PID 32434 INFO: Helper process launched with PID 32435 INFO: Helper process launched with PID 32437 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32464 INFO: Helper process launched with PID 32465 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32499 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32570 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32748 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32767 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 352 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.988 ; free physical = 24353 ; free virtual = 52604 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 24344 ; free virtual = 52596 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 24333 ; free virtual = 52585 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 24331 ; free virtual = 52583 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 24311 ; free virtual = 52563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 24286 ; free virtual = 52538 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 24279 ; free virtual = 52531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 24264 ; free virtual = 52516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 24257 ; free virtual = 52509 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 24166 ; free virtual = 52418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 24133 ; free virtual = 52386 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'idelayctrl' of module 'IDELAYCTRL' requires 3 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-638] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IDELAY_TYPE bound to: FIXED - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'IDELAYE2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y11' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y12' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y15' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y16' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y17' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:83] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y18' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:139] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y21' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y22' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:279] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y23' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:335] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y24' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y25' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y26' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y27' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y28' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y29' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y30' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y3' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y4' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y33' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y34' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y35' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y36' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y39' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y40' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y41' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y42' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y45' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y46' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y47' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:391] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y48' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:447] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y5' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:503] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y6' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:587] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y9' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:643] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y10' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:699] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y100' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y149' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:755] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:811] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y50' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:895] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y99' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:951] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y107' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1007] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y108' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1063] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y119' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1119] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y120' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1203] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y131' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1259] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y132' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1315] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y143' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y144' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1371] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1427] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1511] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1567] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1623] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1679] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1763] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y57' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1819] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y58' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1875] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y69' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1931] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y70' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2015] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2071] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2127] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y81' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2183] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y82' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2239] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y93' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2295] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y94' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2351] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y113' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2407] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y114' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2463] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2547] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2603] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y137' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2659] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y138' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2715] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y63' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y64' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y87' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y88' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y101' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y102' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y103' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y104' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y105' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:16] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 24050 ; free virtual = 52304 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.496 ; free physical = 24114 ; free virtual = 52373 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 24116 ; free virtual = 52371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 24116 ; free virtual = 52371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 24118 ; free virtual = 52372 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 24119 ; free virtual = 52373 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1205.953 ; gain = 110.508 ; free physical = 24128 ; free virtual = 52382 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 24131 ; free virtual = 52386 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 24131 ; free virtual = 52388 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 24131 ; free virtual = 52388 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.496 ; free physical = 24131 ; free virtual = 52389 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.523 ; free physical = 24129 ; free virtual = 52389 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 24139 ; free virtual = 52399 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 24149 ; free virtual = 52404 INFO: [Synth 8-256] done synthesizing module 'LUT6' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dummy_lut' of module 'LUT6' requires 7 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 24148 ; free virtual = 52404 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 24154 ; free virtual = 52410 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (3#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.969 ; gain = 102.531 ; free physical = 24152 ; free virtual = 52408 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 24154 ; free virtual = 52410 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.969 ; gain = 102.531 ; free physical = 24160 ; free virtual = 52416 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 24167 ; free virtual = 52423 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.523 ; free physical = 24165 ; free virtual = 52421 No constraint files found. --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 24206 ; free virtual = 52463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 24213 ; free virtual = 52469 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 24216 ; free virtual = 52474 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 24215 ; free virtual = 52475 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] No constraint files found. WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.953 ; gain = 115.504 ; free physical = 24202 ; free virtual = 52462 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] No constraint files found. WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] Detailed RTL Component Info : +---Registers : WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 24179 ; free virtual = 52435 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 24149 ; free virtual = 52405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 24148 ; free virtual = 52404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 24131 ; free virtual = 52387 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2195] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2322] Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 24103 ; free virtual = 52360 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2405] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2470] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2488] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2654] --------------------------------------------------------------------------------- Start Loading Part and Timing Information WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2693] --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2968] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2986] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3051] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3108] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 24100 ; free virtual = 52357 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3134] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3152] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3191] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3217] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3318] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3383] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3401] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3466] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3484] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3549] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3567] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3632] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3650] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3715] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3733] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3798] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3816] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3881] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3899] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3964] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3982] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4047] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4065] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4104] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4231] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4314] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4397] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4563] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4646] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4729] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4812] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4978] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5061] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5144] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5227] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5476] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5559] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5642] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] ---------------------------------------------------------------------------------WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5725] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5808] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 24090 ; free virtual = 52347 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] ---------------------------------------------------------------------------------WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5891] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5974] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6057] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6223] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6306] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6389] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6472] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6555] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6638] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6721] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6804] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6887] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6970] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7053] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7136] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7219] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7302] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7468] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 24075 ; free virtual = 52332 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 24013 ; free virtual = 52270 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 24009 ; free virtual = 52266 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 23909 ; free virtual = 52167 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 23732 ; free virtual = 51989 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 23676 ; free virtual = 51934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 23674 ; free virtual = 51931 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 23580 ; free virtual = 51837 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 23315 ; free virtual = 51575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 23221 ; free virtual = 51481 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 23220 ; free virtual = 51480 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.691 ; gain = 208.234 ; free physical = 22692 ; free virtual = 50964 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1327.922 ; gain = 232.477 ; free physical = 22674 ; free virtual = 50946 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 22674 ; free virtual = 50946 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.691 ; gain = 208.234 ; free physical = 22680 ; free virtual = 50943 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1327.922 ; gain = 232.477 ; free physical = 22671 ; free virtual = 50933 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 22666 ; free virtual = 50928 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22673 ; free virtual = 50935 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22667 ; free virtual = 50929 Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22664 ; free virtual = 50926 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22666 ; free virtual = 50928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 22663 ; free virtual = 50925 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 22660 ; free virtual = 50922 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 22660 ; free virtual = 50922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 22657 ; free virtual = 50921 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22643 ; free virtual = 50910 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. No constraint files found.--------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 22651 ; free virtual = 50913 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22651 ; free virtual = 50913 --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 22642 ; free virtual = 50905 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22647 ; free virtual = 50909 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22637 ; free virtual = 50899 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22637 ; free virtual = 50899 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 22638 ; free virtual = 50901 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.934 ; gain = 210.480 ; free physical = 22624 ; free virtual = 50892 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.934 ; gain = 210.480 ; free physical = 22626 ; free virtual = 50889 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22622 ; free virtual = 50885 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 22620 ; free virtual = 50883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22618 ; free virtual = 50881 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22618 ; free virtual = 50880 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- No constraint files found. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22617 ; free virtual = 50880 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22617 ; free virtual = 50880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22616 ; free virtual = 50879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22616 ; free virtual = 50879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 22616 ; free virtual = 50879 Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22616 ; free virtual = 50879 Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| --------------------------------------------------------------------------------- |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22617 ; free virtual = 50880 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22617 ; free virtual = 50880 |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22617 ; free virtual = 50880 --------------------------------------------------------------------------------- Report RTL Partitions: Report Check Netlist: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+------------------+-------+---------+-------+------------------+ +-+--------------+------------+----------+ | |Item |Errors |Warnings |Status |Description | +-+--------------+------------+----------+ +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22617 ; free virtual = 50880 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22617 ; free virtual = 50880 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22617 ; free virtual = 50880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22612 ; free virtual = 50875 Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22611 ; free virtual = 50874 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22616 ; free virtual = 50879 --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22616 ; free virtual = 50879 --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22616 ; free virtual = 50879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22616 ; free virtual = 50879 Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ --------------------------------------------------------------------------------- |1 |IN_FIFO | 16| +------+--------+------+ --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |IDELAYCTRL | 1| |2 |IDELAYE2 | 200| |3 |IBUF | 200| +------+-----------+------+ Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22622 ; free virtual = 50885 Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | --------------------------------------------------------------------------------- +------+---------+-------+------+ |1 |top | | 401| +------+---------+-------+------+ --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22618 ; free virtual = 50881 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 402 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 22617 ; free virtual = 50880 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 22618 ; free virtual = 50880 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.945 ; gain = 242.492 ; free physical = 22619 ; free virtual = 50882 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 22622 ; free virtual = 50884 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 22622 ; free virtual = 50885 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.676 ; gain = 216.211 ; free physical = 22624 ; free virtual = 50887 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22593 ; free virtual = 50856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22583 ; free virtual = 50845 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22582 ; free virtual = 50845 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22582 ; free virtual = 50845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22582 ; free virtual = 50845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22582 ; free virtual = 50845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22582 ; free virtual = 50845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22582 ; free virtual = 50844 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22582 ; free virtual = 50844 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22583 ; free virtual = 50846 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22573 ; free virtual = 50836 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22573 ; free virtual = 50835 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22572 ; free virtual = 50834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22571 ; free virtual = 50834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22571 ; free virtual = 50833 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22570 ; free virtual = 50832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22569 ; free virtual = 50832 Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22569 ; free virtual = 50832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22569 ; free virtual = 50832 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22569 ; free virtual = 50832 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 22571 ; free virtual = 50833 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22571 ; free virtual = 50834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22571 ; free virtual = 50834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22571 ; free virtual = 50834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22571 ; free virtual = 50834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22570 ; free virtual = 50833 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. INFO: [Project 1-571] Translating synthesized netlist Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22560 ; free virtual = 50826 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 22559 ; free virtual = 50825 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I1 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I2 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I3 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I4 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I5 to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22558 ; free virtual = 50825 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22557 ; free virtual = 50825 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22557 ; free virtual = 50825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22556 ; free virtual = 50824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22553 ; free virtual = 50821 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22551 ; free virtual = 50819 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT6 | 1| |2 |IBUF | 96| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 97| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22557 ; free virtual = 50820 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 22553 ; free virtual = 50816 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22545 ; free virtual = 50809 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 400 Unisim elements for replacement No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.691 ; gain = 215.238 ; free physical = 22564 ; free virtual = 50827 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22564 ; free virtual = 50827 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22564 ; free virtual = 50827 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22563 ; free virtual = 50826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22563 ; free virtual = 50826 --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22563 ; free virtual = 50826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22563 ; free virtual = 50826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22563 ; free virtual = 50826 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 22563 ; free virtual = 50826 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.918 ; gain = 218.457 ; free physical = 22564 ; free virtual = 50828 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.691 ; gain = 215.238 ; free physical = 22534 ; free virtual = 50797 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22531 ; free virtual = 50794 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22524 ; free virtual = 50788 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22529 ; free virtual = 50793 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22528 ; free virtual = 50791 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22528 ; free virtual = 50791 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22526 ; free virtual = 50789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22526 ; free virtual = 50789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22526 ; free virtual = 50789 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. INFO: [Project 1-570] Preparing netlist for logic optimization Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 22524 ; free virtual = 50787 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22526 ; free virtual = 50789 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22394 ; free virtual = 50658 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22393 ; free virtual = 50657 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22393 ; free virtual = 50657 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22394 ; free virtual = 50658 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22394 ; free virtual = 50658 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22394 ; free virtual = 50658 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22394 ; free virtual = 50658 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 22394 ; free virtual = 50658 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.691 ; gain = 225.230 ; free physical = 22397 ; free virtual = 50661 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1398.684 ; gain = 315.797 ; free physical = 21873 ; free virtual = 50138 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1396.688 ; gain = 313.797 ; free physical = 21872 ; free virtual = 50138 INFO: [DRC 23-27] Running DRC with 8 threads Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y0' at site IDELAY_X0Y0, Site IOB_X0Y0 is not bonded. Place terminal di[0] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y1' at site IDELAY_X0Y1, Site IOB_X0Y1 is not bonded. Place terminal di[14] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y2' at site IDELAY_X0Y2, Site IOB_X0Y2 is not bonded. Place terminal di[15] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] Command: report_drc (run_mandatory_drcs) for: incr_eco_checks CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y29' at site IDELAY_X0Y29, Site IOB_X0Y29 is not bonded. Place terminal di[30] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y3' at site IDELAY_X0Y3, Site IOB_X0Y3 is not bonded. Place terminal di[32] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y30' at site IDELAY_X0Y30, Site IOB_X0Y30 is not bonded. Place terminal di[31] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y31' at site IDELAY_X0Y31, Site IOB_X0Y31 is not bonded. Place terminal di[4] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y32' at site IDELAY_X0Y32, Site IOB_X0Y32 is not bonded. Place terminal di[5] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y33' at site IDELAY_X0Y33, Site IOB_X0Y33 is not bonded. Place terminal di[34] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y34' at site IDELAY_X0Y34, Site IOB_X0Y34 is not bonded. Place terminal di[35] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y35' at site IDELAY_X0Y35, Site IOB_X0Y35 is not bonded. Place terminal di[36] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y36' at site IDELAY_X0Y36, Site IOB_X0Y36 is not bonded. Place terminal di[37] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y38' at site IDELAY_X0Y38, Site IOB_X0Y38 is not bonded. Place terminal di[13] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y39' at site IDELAY_X0Y39, Site IOB_X0Y39 is not bonded. Place terminal di[38] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y4' at site IDELAY_X0Y4, Site IOB_X0Y4 is not bonded. Place terminal di[33] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y40' at site IDELAY_X0Y40, Site IOB_X0Y40 is not bonded. Place terminal di[39] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y41' at site IDELAY_X0Y41, Site IOB_X0Y41 is not bonded. Place terminal di[40] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y42' at site IDELAY_X0Y42, Site IOB_X0Y42 is not bonded. Place terminal di[41] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y43' at site IDELAY_X0Y43, Site IOB_X0Y43 is not bonded. Place terminal di[6] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y44' at site IDELAY_X0Y44, Site IOB_X0Y44 is not bonded. Place terminal di[7] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y45' at site IDELAY_X0Y45, Site IOB_X0Y45 is not bonded. Place terminal di[42] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y46' at site IDELAY_X0Y46, Site IOB_X0Y46 is not bonded. Place terminal di[43] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y47' at site IDELAY_X0Y47, Site IOB_X0Y47 is not bonded. Place terminal di[44] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y48' at site IDELAY_X0Y48, Site IOB_X0Y48 is not bonded. Place terminal di[45] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y49' at site IDELAY_X0Y49, Site IOB_X0Y49 is not bonded. Place terminal di[1] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y0' at site IDELAY_X1Y0, Site IOB_X1Y0 is not bonded. Place terminal di[50] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y1' at site IDELAY_X1Y1, Site IOB_X1Y1 is not bonded. Place terminal di[92] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y10' at site IDELAY_X1Y10, Site IOB_X1Y10 is not bonded. Place terminal di[193] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2335] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y11' at site IDELAY_X1Y11, Site IOB_X1Y11 is not bonded. Place terminal di[102] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1243] INFO: [DRC 23-27] Running DRC with 8 threads CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y12' at site IDELAY_X1Y12, Site IOB_X1Y12 is not bonded. Place terminal di[103] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1255] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y13' at site IDELAY_X1Y13, Site IOB_X1Y13 is not bonded. Place terminal di[82] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y14' at site IDELAY_X1Y14, Site IOB_X1Y14 is not bonded. Place terminal di[83] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y15' at site IDELAY_X1Y15, Site IOB_X1Y15 is not bonded. Place terminal di[132] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1603] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y16' at site IDELAY_X1Y16, Site IOB_X1Y16 is not bonded. Place terminal di[133] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1615] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y17' at site IDELAY_X1Y17, Site IOB_X1Y17 is not bonded. Place terminal di[134] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1627] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y18' at site IDELAY_X1Y18, Site IOB_X1Y18 is not bonded. Place terminal di[135] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1639] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y19' at site IDELAY_X1Y19, Site IOB_X1Y19 is not bonded. Place terminal di[64] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y2' at site IDELAY_X1Y2, Site IOB_X1Y2 is not bonded. Place terminal di[93] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y20' at site IDELAY_X1Y20, Site IOB_X1Y20 is not bonded. Place terminal di[65] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y21' at site IDELAY_X1Y21, Site IOB_X1Y21 is not bonded. Place terminal di[136] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1651] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y22' at site IDELAY_X1Y22, Site IOB_X1Y22 is not bonded. Place terminal di[137] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1663] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y23' at site IDELAY_X1Y23, Site IOB_X1Y23 is not bonded. Place terminal di[138] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1675] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y24' at site IDELAY_X1Y24, Site IOB_X1Y24 is not bonded. Place terminal di[139] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1687] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y25' at site IDELAY_X1Y25, Site IOB_X1Y25 is not bonded. Place terminal di[140] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1699] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y26' at site IDELAY_X1Y26, Site IOB_X1Y26 is not bonded. Place terminal di[141] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1711] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y27' at site IDELAY_X1Y27, Site IOB_X1Y27 is not bonded. Place terminal di[142] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1723] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y28' at site IDELAY_X1Y28, Site IOB_X1Y28 is not bonded. Place terminal di[143] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1735] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y29' at site IDELAY_X1Y29, Site IOB_X1Y29 is not bonded. Place terminal di[144] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1747] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y3' at site IDELAY_X1Y3, Site IOB_X1Y3 is not bonded. Place terminal di[146] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1771] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y30' at site IDELAY_X1Y30, Site IOB_X1Y30 is not bonded. Place terminal di[145] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1759] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y31' at site IDELAY_X1Y31, Site IOB_X1Y31 is not bonded. Place terminal di[66] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y32' at site IDELAY_X1Y32, Site IOB_X1Y32 is not bonded. Place terminal di[67] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y33' at site IDELAY_X1Y33, Site IOB_X1Y33 is not bonded. Place terminal di[148] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1795] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y34' at site IDELAY_X1Y34, Site IOB_X1Y34 is not bonded. Place terminal di[149] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1807] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y35' at site IDELAY_X1Y35, Site IOB_X1Y35 is not bonded. Place terminal di[150] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1819] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y36' at site IDELAY_X1Y36, Site IOB_X1Y36 is not bonded. Place terminal di[151] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1831] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y37' at site IDELAY_X1Y37, Site IOB_X1Y37 is not bonded. Place terminal di[86] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y38' at site IDELAY_X1Y38, Site IOB_X1Y38 is not bonded. Place terminal di[87] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y39' at site IDELAY_X1Y39, Site IOB_X1Y39 is not bonded. Place terminal di[152] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1843] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y4' at site IDELAY_X1Y4, Site IOB_X1Y4 is not bonded. Place terminal di[147] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1783] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y40' at site IDELAY_X1Y40, Site IOB_X1Y40 is not bonded. Place terminal di[153] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1855] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y41' at site IDELAY_X1Y41, Site IOB_X1Y41 is not bonded. Place terminal di[154] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1867] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y42' at site IDELAY_X1Y42, Site IOB_X1Y42 is not bonded. Place terminal di[155] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1879] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y43' at site IDELAY_X1Y43, Site IOB_X1Y43 is not bonded. Place terminal di[68] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y44' at site IDELAY_X1Y44, Site IOB_X1Y44 is not bonded. Place terminal di[69] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y45' at site IDELAY_X1Y45, Site IOB_X1Y45 is not bonded. Place terminal di[156] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1891] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y46' at site IDELAY_X1Y46, Site IOB_X1Y46 is not bonded. Place terminal di[157] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1903] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y47' at site IDELAY_X1Y47, Site IOB_X1Y47 is not bonded. Place terminal di[158] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1915] Command: report_drc (run_mandatory_drcs) for: placer_checks CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y48' at site IDELAY_X1Y48, Site IOB_X1Y48 is not bonded. Place terminal di[159] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1927] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y49' at site IDELAY_X1Y49, Site IOB_X1Y49 is not bonded. Place terminal di[53] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y5' at site IDELAY_X1Y5, Site IOB_X1Y5 is not bonded. Place terminal di[160] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1939] INFO: [DRC 23-27] Running DRC with 8 threads CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y6' at site IDELAY_X1Y6, Site IOB_X1Y6 is not bonded. Place terminal di[161] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1951] --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y7' at site IDELAY_X1Y7, Site IOB_X1Y7 is not bonded. Place terminal di[74] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 21830 ; free virtual = 50096 --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y8' at site IDELAY_X1Y8, Site IOB_X1Y8 is not bonded. Place terminal di[75] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y9' at site IDELAY_X1Y9, Site IOB_X1Y9 is not bonded. Place terminal di[192] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2323] INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-570] Preparing netlist for logic optimization Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1420.938 ; gain = 338.047 ; free physical = 21879 ; free virtual = 50144 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1401.680 ; gain = 318.797 ; free physical = 21888 ; free virtual = 50154 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads 18 Infos, 200 Warnings, 75 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1399.691 ; gain = 316.797 ; free physical = 21902 ; free virtual = 50168 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads Looping INT_L_X0Y0 0 IDELAY_X0Y0 IOB_X0Y0 {di[0]} key "IOB_X0Y0" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl" line 75) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:54:35 2019... --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 21891 ; free virtual = 50157 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 21980 ; free virtual = 50245 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 21979 ; free virtual = 50245 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' Makefile:60: recipe for target 'iob_int/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task 14 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1395.715 ; gain = 312.828 ; free physical = 22323 ; free virtual = 50592 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.711 ; gain = 0.000 ; free physical = 22316 ; free virtual = 50585 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1465.711 ; gain = 0.000 ; free physical = 22315 ; free virtual = 50585 Looping LIOB33_X0Y1 0 IOB_X0Y1 {di[0]} key "IOB_X0Y1" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl" line 77) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:54:35 2019... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22320 ; free virtual = 50594 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' Makefile:57: recipe for target 'iob/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 22650 ; free virtual = 50935 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 22648 ; free virtual = 50934 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 22664 ; free virtual = 50950 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 22631 ; free virtual = 50899 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.969 ; gain = 0.000 ; free physical = 22631 ; free virtual = 50899 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1484.969 ; gain = 0.000 ; free physical = 22631 ; free virtual = 50899 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1404.934 ; gain = 322.039 ; free physical = 22737 ; free virtual = 51005 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22824 ; free virtual = 51092 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22824 ; free virtual = 51092 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22807 ; free virtual = 51085 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22807 ; free virtual = 51088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22801 ; free virtual = 51087 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22797 ; free virtual = 51085 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22796 ; free virtual = 51083 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 22795 ; free virtual = 51082 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 22792 ; free virtual = 51079 INFO: [Project 1-571] Translating synthesized netlist 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 22780 ; free virtual = 51068 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22698 ; free virtual = 50986 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1583c4629 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22696 ; free virtual = 50984 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 22690 ; free virtual = 50958 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 22690 ; free virtual = 50958 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.965 ; gain = 0.000 ; free physical = 22673 ; free virtual = 50942 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1470.965 ; gain = 0.000 ; free physical = 22673 ; free virtual = 50942 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 22626 ; free virtual = 50895 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 22619 ; free virtual = 50888 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-570] Preparing netlist for logic optimization 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 22602 ; free virtual = 50871 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 22510 ; free virtual = 50780 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 22509 ; free virtual = 50779 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1335.066 ; gain = 239.152 ; free physical = 22234 ; free virtual = 50506 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 1345.098 ; gain = 249.184 ; free physical = 22096 ; free virtual = 50371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1345.098 ; gain = 249.184 ; free physical = 22067 ; free virtual = 50342 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 22024 ; free virtual = 50300 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21930 ; free virtual = 50205 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.289 ; gain = 0.000 ; free physical = 21926 ; free virtual = 50203 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1549.289 ; gain = 0.000 ; free physical = 21916 ; free virtual = 50192 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21892 ; free virtual = 50169 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21888 ; free virtual = 50165 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21878 ; free virtual = 50155 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21876 ; free virtual = 50153 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21873 ; free virtual = 50151 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21872 ; free virtual = 50150 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21872 ; free virtual = 50150 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 21871 ; free virtual = 50149 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1353.082 ; gain = 257.160 ; free physical = 21873 ; free virtual = 50150 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.199 ; gain = 0.000 ; free physical = 21153 ; free virtual = 49433 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.242 ; gain = 435.531 ; free physical = 21040 ; free virtual = 49320 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.242 ; gain = 435.531 ; free physical = 21014 ; free virtual = 49294 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.242 ; gain = 435.531 ; free physical = 21013 ; free virtual = 49293 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.242 ; gain = 435.531 ; free physical = 21012 ; free virtual = 49292 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.242 ; gain = 435.531 ; free physical = 21011 ; free virtual = 49291 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.242 ; gain = 435.531 ; free physical = 21008 ; free virtual = 49288 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.242 ; gain = 499.562 ; free physical = 21008 ; free virtual = 49288 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.207 ; gain = 0.000 ; free physical = 20521 ; free virtual = 48800 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.457 ; gain = 0.000 ; free physical = 20445 ; free virtual = 48725 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20416 ; free virtual = 48696 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20397 ; free virtual = 48676 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20396 ; free virtual = 48676 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20396 ; free virtual = 48676 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20395 ; free virtual = 48675 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20394 ; free virtual = 48674 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 507.562 ; free physical = 20394 ; free virtual = 48673 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.203 ; gain = 0.000 ; free physical = 20239 ; free virtual = 48519 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 20194 ; free virtual = 48474 Phase 1.3 Build Placer Netlist Model ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 20172 ; free virtual = 48453 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 20171 ; free virtual = 48451 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 20169 ; free virtual = 48450 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 19650 ; free virtual = 47930 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 19640 ; free virtual = 47920 Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 19641 ; free virtual = 47921 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 19639 ; free virtual = 47920 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 19638 ; free virtual = 47918 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 19635 ; free virtual = 47916 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 19632 ; free virtual = 47913 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.246 ; gain = 532.562 ; free physical = 19632 ; free virtual = 47913 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.453 ; gain = 0.000 ; free physical = 19536 ; free virtual = 47817 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 19425 ; free virtual = 47706 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 19373 ; free virtual = 47654 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 19378 ; free virtual = 47660 Phase 1 Placer Initialization | Checksum: bca60bcf INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 19375 ; free virtual = 47656 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 19365 ; free virtual = 47646 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 19366 ; free virtual = 47648 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.496 ; gain = 581.562 ; free physical = 19365 ; free virtual = 47646 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b00cead Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19260 ; free virtual = 47542 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19238 ; free virtual = 47520 Phase 1.4 Constrain Clocks/Macros INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.4 Constrain Clocks/Macros | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19234 ; free virtual = 47516 Phase 1 Placer Initialization | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19232 ; free virtual = 47514 Phase 2 Global Placement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1609 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 19244 ; free virtual = 47526 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Routing Task Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 19089 ; free virtual = 47372 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 19069 ; free virtual = 47351 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 19048 ; free virtual = 47331 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2056 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 19023 ; free virtual = 47306 report_drc (run_mandatory_drcs) completed successfully Phase 2 Final Placement Cleanup INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 19001 ; free virtual = 47283 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 18978 ; free virtual = 47260 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 18977 ; free virtual = 47259 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18900 ; free virtual = 47184 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.234 ; gain = 0.000 ; free physical = 18894 ; free virtual = 47177 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18894 ; free virtual = 47177 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18889 ; free virtual = 47172 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18891 ; free virtual = 47174 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18891 ; free virtual = 47174 Phase 3.5 Small Shape Detail Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 18869 ; free virtual = 47152 Phase 1.3 Build Placer Netlist Model WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 18857 ; free virtual = 47141 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 18851 ; free virtual = 47135 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 18846 ; free virtual = 47130 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 18839 ; free virtual = 47123 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 18841 ; free virtual = 47125 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.277 ; gain = 577.562 ; free physical = 18838 ; free virtual = 47122 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18840 ; free virtual = 47124 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18840 ; free virtual = 47124 Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks Phase 3.7 Pipeline Register Optimization INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18840 ; free virtual = 47123 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18840 ; free virtual = 47123 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18838 ; free virtual = 47121 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18828 ; free virtual = 47111 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18827 ; free virtual = 47111 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18827 ; free virtual = 47111 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18827 ; free virtual = 47110 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 18842 ; free virtual = 47126 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.547 ; gain = 614.609 ; free physical = 18842 ; free virtual = 47126 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18741 ; free virtual = 47025 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18742 ; free virtual = 47027 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d4686e25 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18742 ; free virtual = 47027 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ae434bf0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18776 ; free virtual = 47061 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 177f7ac55 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18774 ; free virtual = 47060 Phase 3.5 Small Shape Detail Placement WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.5 Small Shape Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18770 ; free virtual = 47055 Phase 3.6 Re-assign LUT pins Starting Routing Task Starting Routing Task Phase 3.6 Re-assign LUT pins | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18770 ; free virtual = 47055 Phase 3.7 Pipeline Register Optimization INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.7 Pipeline Register Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18769 ; free virtual = 47054 Phase 3 Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18769 ; free virtual = 47054 Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18767 ; free virtual = 47052 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18753 ; free virtual = 47039 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18721 ; free virtual = 47006 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18718 ; free virtual = 47004 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18715 ; free virtual = 47000 Ending Placer Task | Checksum: 1c0d5e9dc Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18726 ; free virtual = 47012 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 18726 ; free virtual = 47011 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: dc3640d2 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 18081 ; free virtual = 46371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 17765 ; free virtual = 46055 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1905.777 ; gain = 0.000 ; free physical = 17666 ; free virtual = 45958 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 17672 ; free virtual = 45963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 17613 ; free virtual = 45905 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 17613 ; free virtual = 45905 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 17613 ; free virtual = 45905 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 17487 ; free virtual = 45780 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 17462 ; free virtual = 45755 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 17476 ; free virtual = 45769 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 17476 ; free virtual = 45769 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.492 ; gain = 454.203 ; free physical = 17386 ; free virtual = 45679 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1476.832 ; gain = 393.945 ; free physical = 17322 ; free virtual = 45617 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.492 ; gain = 454.203 ; free physical = 17216 ; free virtual = 45512 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.492 ; gain = 454.203 ; free physical = 17212 ; free virtual = 45509 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.492 ; gain = 454.203 ; free physical = 17209 ; free virtual = 45505 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1555.863 ; gain = 0.000 ; free physical = 17170 ; free virtual = 45467 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.62 . Memory (MB): peak = 1555.863 ; gain = 0.000 ; free physical = 17156 ; free virtual = 45454 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 17107 ; free virtual = 45404 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 17103 ; free virtual = 45401 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17103 ; free virtual = 45401 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 17087 ; free virtual = 45386 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 17086 ; free virtual = 45385 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17085 ; free virtual = 45383 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 17085 ; free virtual = 45383 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17084 ; free virtual = 45382 --------------------------------------------------------------------------------- Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17083 ; free virtual = 45382 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17083 ; free virtual = 45382 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17083 ; free virtual = 45381 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17083 ; free virtual = 45381 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17083 ; free virtual = 45381 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17083 ; free virtual = 45381 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17083 ; free virtual = 45381 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 17084 ; free virtual = 45383 INFO: [Project 1-571] Translating synthesized netlist Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 17068 ; free virtual = 45367 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 17021 ; free virtual = 45321 Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17015 ; free virtual = 45314 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17014 ; free virtual = 45314 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17014 ; free virtual = 45314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17014 ; free virtual = 45314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17014 ; free virtual = 45314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17014 ; free virtual = 45314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17014 ; free virtual = 45314 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 17014 ; free virtual = 45313 Phase 3.4 Pipeline Register Optimization Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17012 ; free virtual = 45312 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17015 ; free virtual = 45314 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16994 ; free virtual = 45294 Phase 3.5 Small Shape Detail Placement INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16942 ; free virtual = 45243 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16935 ; free virtual = 45236 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16913 ; free virtual = 45214 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16890 ; free virtual = 45191 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16874 ; free virtual = 45176 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16860 ; free virtual = 45162 Phase 4.3 Placer Reporting INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16792 ; free virtual = 45094 Phase 4.4 Final Placement Cleanup 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1396.691 ; gain = 313.797 ; free physical = 16819 ; free virtual = 45122 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16799 ; free virtual = 45102 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16786 ; free virtual = 45088 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.723 ; gain = 0.000 ; free physical = 16812 ; free virtual = 45115 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1460.723 ; gain = 0.000 ; free physical = 16812 ; free virtual = 45115 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.539 ; gain = 550.250 ; free physical = 16810 ; free virtual = 45112 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.539 ; gain = 632.281 ; free physical = 16810 ; free virtual = 45112 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 16777 ; free virtual = 45081 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 16828 ; free virtual = 45131 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 16828 ; free virtual = 45131 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: a00a49b6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2055.934 ; gain = 119.668 ; free physical = 16228 ; free virtual = 44540 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1 Build RT Design | Checksum: e50efac9 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2053.926 ; gain = 120.668 ; free physical = 16224 ; free virtual = 44536 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a00a49b6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 16188 ; free virtual = 44500 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a00a49b6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 16188 ; free virtual = 44500 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e50efac9 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2058.914 ; gain = 125.656 ; free physical = 16157 ; free virtual = 44469 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e50efac9 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2058.914 ; gain = 125.656 ; free physical = 16157 ; free virtual = 44469 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16160 ; free virtual = 44472 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e90f676 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16159 ; free virtual = 44471 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16166 ; free virtual = 44479 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16166 ; free virtual = 44478 Phase 4 Rip-up And Reroute | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16166 ; free virtual = 44478 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16166 ; free virtual = 44478 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16166 ; free virtual = 44478 Phase 6 Post Hold Fix | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16166 ; free virtual = 44478 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 7 Route finalize Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e90f676 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16165 ; free virtual = 44478 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16165 ; free virtual = 44477 Phase 4 Rip-up And Reroute | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16165 ; free virtual = 44477 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16165 ; free virtual = 44477 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16165 ; free virtual = 44477 Phase 6 Post Hold Fix | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16165 ; free virtual = 44477 Phase 7 Route finalize Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 16164 ; free virtual = 44477 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 16163 ; free virtual = 44476 Phase 9 Depositing Routes Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 9 Depositing Routes | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 16163 ; free virtual = 44476 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 16200 ; free virtual = 44513 Routing Is Done. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2108.766 ; gain = 204.516 ; free physical = 16200 ; free virtual = 44513 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.969 ; gain = 132.711 ; free physical = 16201 ; free virtual = 44514 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 135.711 ; free physical = 16201 ; free virtual = 44513 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 135.711 ; free physical = 16201 ; free virtual = 44514 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 135.711 ; free physical = 16234 ; free virtual = 44547 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2107.758 ; gain = 206.516 ; free physical = 16234 ; free virtual = 44547 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1963.352 ; gain = 0.000 ; free physical = 16232 ; free virtual = 44545 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 16226 ; free virtual = 44540 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2107.758 ; gain = 0.000 ; free physical = 16215 ; free virtual = 44531 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2055.930 ; gain = 92.668 ; free physical = 16129 ; free virtual = 44443 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 97.656 ; free physical = 16054 ; free virtual = 44368 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 97.656 ; free physical = 16053 ; free virtual = 44366 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 16098 ; free virtual = 44412 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 16114 ; free virtual = 44428 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 16111 ; free virtual = 44426 Phase 4 Rip-up And Reroute | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 16111 ; free virtual = 44425 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 16111 ; free virtual = 44425 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 16111 ; free virtual = 44425 Phase 6 Post Hold Fix | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 16111 ; free virtual = 44425 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 16093 ; free virtual = 44408 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.973 ; gain = 107.711 ; free physical = 16092 ; free virtual = 44407 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.973 ; gain = 107.711 ; free physical = 16094 ; free virtual = 44409 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.973 ; gain = 107.711 ; free physical = 16128 ; free virtual = 44442 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2109.762 ; gain = 178.516 ; free physical = 16128 ; free virtual = 44442 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2063.180 ; gain = 44.668 ; free physical = 16125 ; free virtual = 44439 Writing placer database... Writing XDEF routing. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 16094 ; free virtual = 44410 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.168 ; gain = 49.656 ; free physical = 16092 ; free virtual = 44408 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.168 ; gain = 49.656 ; free physical = 16092 ; free virtual = 44408 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2051.395 ; gain = 495.531 ; free physical = 16096 ; free virtual = 44412 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2078.223 ; gain = 59.711 ; free physical = 16041 ; free virtual = 44356 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 16080 ; free virtual = 44396 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 16093 ; free virtual = 44408 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 16101 ; free virtual = 44417 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 16104 ; free virtual = 44419 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 16104 ; free virtual = 44420 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 16102 ; free virtual = 44417 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 16073 ; free virtual = 44389 Phase 8 Verifying routed nets Verification completed successfully Running DRC as a precondition to command write_bitstream Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2082.223 ; gain = 63.711 ; free physical = 16077 ; free virtual = 44393 Phase 9 Depositing Routes Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2082.223 ; gain = 63.711 ; free physical = 16095 ; free virtual = 44411 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2082.223 ; gain = 63.711 ; free physical = 16129 ; free virtual = 44445 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2121.012 ; gain = 134.516 ; free physical = 16129 ; free virtual = 44444 Writing placer database... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.172 ; gain = 44.668 ; free physical = 16129 ; free virtual = 44445 Writing XDEF routing. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2121.012 ; gain = 0.000 ; free physical = 16106 ; free virtual = 44424 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.160 ; gain = 51.656 ; free physical = 16048 ; free virtual = 44367 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.160 ; gain = 51.656 ; free physical = 16038 ; free virtual = 44357 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16014 ; free virtual = 44331 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 15824 ; free virtual = 44142 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 15825 ; free virtual = 44143 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 15826 ; free virtual = 44144 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 15833 ; free virtual = 44151 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 15841 ; free virtual = 44158 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 15846 ; free virtual = 44164 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 15853 ; free virtual = 44171 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 15846 ; free virtual = 44165 Phase 9 Depositing Routes Running DRC as a precondition to command write_bitstream Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 15852 ; free virtual = 44170 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 15880 ; free virtual = 44198 Routing Is Done. Command: report_drc (run_mandatory_drcs) for: bitstream_checks 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.254 ; gain = 137.766 ; free physical = 15875 ; free virtual = 44193 INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing placer database... Phase 1 Build RT Design | Checksum: edf89240 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.961 ; gain = 41.668 ; free physical = 15812 ; free virtual = 44131 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: edf89240 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.949 ; gain = 47.656 ; free physical = 15721 ; free virtual = 44042 Phase 2.2 Pre Route Cleanup Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 15710 ; free virtual = 44032 Phase 2.2 Pre Route Cleanup | Checksum: edf89240 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.949 ; gain = 47.656 ; free physical = 15708 ; free virtual = 44029 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1446d92b6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.379 ; gain = 60.086 ; free physical = 15504 ; free virtual = 43824 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.211 ; gain = 0.000 ; free physical = 15469 ; free virtual = 43788 Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.188 ; gain = 34.641 ; free physical = 15472 ; free virtual = 43792 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.176 ; gain = 39.629 ; free physical = 15442 ; free virtual = 43762 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.176 ; gain = 39.629 ; free physical = 15441 ; free virtual = 43761 Number of Nodes with overlaps = 0 Loading data files... Phase 3 Initial Routing | Checksum: 1446d92b6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 15428 ; free virtual = 43748 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 15443 ; free virtual = 43763 Phase 1.3 Build Placer Netlist Model Phase 4.1 Global Iteration 0 | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 15443 ; free virtual = 43763 Phase 4 Rip-up And Reroute | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 15446 ; free virtual = 43766 Phase 5 Delay and Skew Optimization Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 15448 ; free virtual = 43768 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 15449 ; free virtual = 43769 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 15449 ; free virtual = 43769 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 15449 ; free virtual = 43769 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 5 Delay and Skew Optimization | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 15449 ; free virtual = 43769 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 15451 ; free virtual = 43771 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.254 ; gain = 507.562 ; free physical = 15451 ; free virtual = 43771 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 6.1 Hold Fix Iter | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 15450 ; free virtual = 43770 Phase 6 Post Hold Fix | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 15445 ; free virtual = 43766 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.Running DRC as a precondition to command write_bitstream East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 15356 ; free virtual = 43676 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 15324 ; free virtual = 43644 Phase 9 Depositing Routes Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15229 ; free virtual = 43550 Phase 3 Initial Routing Phase 9 Depositing Routes | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 15216 ; free virtual = 43536 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 15254 ; free virtual = 43575 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.168 ; gain = 134.891 ; free physical = 15253 ; free virtual = 43573 Writing placer database... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15133 ; free virtual = 43455 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15133 ; free virtual = 43454 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15143 ; free virtual = 43464 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15153 ; free virtual = 43475 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15153 ; free virtual = 43475 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15153 ; free virtual = 43475 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Phase 7 Route finalize Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.395 ; gain = 495.531 ; free physical = 15157 ; free virtual = 43479 Phase 1.4 Constrain Clocks/Macros Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15126 ; free virtual = 43450 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15116 ; free virtual = 43440 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15115 ; free virtual = 43438 Write XDEF Complete: Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2129.168 ; gain = 0.000 ; free physical = 15141 ; free virtual = 43465 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 15138 ; free virtual = 43462 Routing Is Done. 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2134.020 ; gain = 98.473 ; free physical = 15137 ; free virtual = 43462 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.395 ; gain = 495.531 ; free physical = 15151 ; free virtual = 43476 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 15144 ; free virtual = 43469 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2134.020 ; gain = 0.000 ; free physical = 15100 ; free virtual = 43423 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.395 ; gain = 495.531 ; free physical = 15078 ; free virtual = 43401 Phase 2 Final Placement Cleanup INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 15065 ; free virtual = 43387 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 15078 ; free virtual = 43401 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 15078 ; free virtual = 43401 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 15078 ; free virtual = 43401 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 15079 ; free virtual = 43402 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 15081 ; free virtual = 43404 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 15081 ; free virtual = 43404 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.395 ; gain = 495.531 ; free physical = 15012 ; free virtual = 43335 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Loading data files... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.395 ; gain = 495.531 ; free physical = 14922 ; free virtual = 43244 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. place_design completed successfully INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2051.395 ; gain = 574.562 ; free physical = 14948 ; free virtual = 43271 INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Command: route_design INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 14974 ; free virtual = 43297 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Running DRC as a precondition to command write_bitstream Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 14944 ; free virtual = 43267 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 14946 ; free virtual = 43269 Command: report_drc (run_mandatory_drcs) for: bitstream_checks Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b9dafcfc Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14791 ; free virtual = 43116 Phase 3 Initial Routing Loading data files... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14719 ; free virtual = 43044 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14710 ; free virtual = 43035 Phase 4 Rip-up And Reroute | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14710 ; free virtual = 43035 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14710 ; free virtual = 43035 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14710 ; free virtual = 43035 Phase 6 Post Hold Fix | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14710 ; free virtual = 43034 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14705 ; free virtual = 43030 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14708 ; free virtual = 43034 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14723 ; free virtual = 43049 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 14759 ; free virtual = 43084 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2142.020 ; gain = 49.473 ; free physical = 14759 ; free virtual = 43084 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2142.020 ; gain = 0.000 ; free physical = 14688 ; free virtual = 43016 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Creating bitstream... Loading data files... Loading route data... Processing options... Creating bitmap... Creating bitstream... Loading site data... Loading site data... Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... Loading site data... Creating bitstream... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2451.832 ; gain = 343.066 ; free physical = 13052 ; free virtual = 41398 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:08 2019... Writing bitstream ./design.bit... Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 Creating bitstream... Loading route data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. Processing options... INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitmap... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:10 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 2450.863 ; gain = 343.105 ; free physical = 14251 ; free virtual = 42602 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:10 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Loading site data... Writing bitstream ./design.bit... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 2452.867 ; gain = 343.105 ; free physical = 15517 ; free virtual = 43885 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:12 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK Writing bitstream ./design.bit... GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2462.430 ; gain = 334.176 ; free physical = 17007 ; free virtual = 45375 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:15 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 2465.125 ; gain = 331.105 ; free physical = 17990 ; free virtual = 46359 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:17 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.766 ; gain = 30.227 ; free physical = 19004 ; free virtual = 47374 touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_002 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.754 ; gain = 36.215 ; free physical = 18970 ; free virtual = 47339 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.754 ; gain = 36.215 ; free physical = 18969 ; free virtual = 47338 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2461.117 ; gain = 340.105 ; free physical = 18949 ; free virtual = 47318 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:18 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19352 ; free virtual = 47722 Phase 3 Initial Routing Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19986 ; free virtual = 48357 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19983 ; free virtual = 48354 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19983 ; free virtual = 48354 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19983 ; free virtual = 48354 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19983 ; free virtual = 48354 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19983 ; free virtual = 48354 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19988 ; free virtual = 48359 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19987 ; free virtual = 48358 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 19986 ; free virtual = 48357 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 20020 ; free virtual = 48391 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2193.598 ; gain = 94.059 ; free physical = 20020 ; free virtual = 48391 Creating bitstream... Writing placer database... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.598 ; gain = 0.000 ; free physical = 20578 ; free virtual = 48982 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:23 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 2470.273 ; gain = 341.105 ; free physical = 20536 ; free virtual = 48919 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:23 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:25 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2475.125 ; gain = 333.105 ; free physical = 21413 ; free virtual = 49800 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:25 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1 Build RT Design | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2056.938 ; gain = 120.668 ; free physical = 21834 ; free virtual = 50225 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2060.926 ; gain = 124.656 ; free physical = 21799 ; free virtual = 50190 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2060.926 ; gain = 124.656 ; free physical = 21798 ; free virtual = 50189 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21781 ; free virtual = 50173 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21758 ; free virtual = 50149 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21756 ; free virtual = 50147 Phase 4 Rip-up And Reroute | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21756 ; free virtual = 50147 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21756 ; free virtual = 50147 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21756 ; free virtual = 50147 Phase 6 Post Hold Fix | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21755 ; free virtual = 50147 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 21750 ; free virtual = 50141 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.980 ; gain = 133.711 ; free physical = 21749 ; free virtual = 50140 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.980 ; gain = 133.711 ; free physical = 21748 ; free virtual = 50140 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.980 ; gain = 133.711 ; free physical = 21781 ; free virtual = 50172 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2108.770 ; gain = 204.516 ; free physical = 21781 ; free virtual = 50172 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2108.770 ; gain = 0.000 ; free physical = 21750 ; free virtual = 50143 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4634 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4669 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2055.930 ; gain = 119.668 ; free physical = 21602 ; free virtual = 49995 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 21543 ; free virtual = 49937 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 21543 ; free virtual = 49936 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4719 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1481dbb17 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21568 ; free virtual = 49962 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21492 ; free virtual = 49886 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21474 ; free virtual = 49868 Phase 4 Rip-up And Reroute | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21472 ; free virtual = 49866 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21471 ; free virtual = 49865 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21470 ; free virtual = 49864 Phase 6 Post Hold Fix | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21470 ; free virtual = 49864 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 21431 ; free virtual = 49825 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 21429 ; free virtual = 49823 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 21428 ; free virtual = 49822 Phase 1 Build RT Design | Checksum: e91ff6d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2135.078 ; gain = 51.668 ; free physical = 21434 ; free virtual = 49828 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 21459 ; free virtual = 49853 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2108.762 ; gain = 204.516 ; free physical = 21459 ; free virtual = 49853 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2108.762 ; gain = 0.000 ; free physical = 21458 ; free virtual = 49854 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e91ff6d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.066 ; gain = 60.656 ; free physical = 21361 ; free virtual = 49756 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e91ff6d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.066 ; gain = 60.656 ; free physical = 21352 ; free virtual = 49746 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18fae605e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21203 ; free virtual = 49598 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21196 ; free virtual = 49591 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21138 ; free virtual = 49533 Phase 4 Rip-up And Reroute | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21119 ; free virtual = 49514 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21093 ; free virtual = 49488 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21076 ; free virtual = 49472 Phase 6 Post Hold Fix | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21135 ; free virtual = 49530 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading route data... Processing options... Creating bitmap... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4772 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21035 ; free virtual = 49431 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21045 ; free virtual = 49441 Phase 9 Depositing Routes Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 9 Depositing Routes | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21097 ; free virtual = 49492 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 21135 ; free virtual = 49531 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:48 . Memory (MB): peak = 2218.285 ; gain = 166.891 ; free physical = 21132 ; free virtual = 49528 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4836 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4873 Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.285 ; gain = 0.000 ; free physical = 20631 ; free virtual = 49058 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20558 ; free virtual = 48987 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 20522 ; free virtual = 48925 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20665 ; free virtual = 49073 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 20680 ; free virtual = 49088 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 20616 ; free virtual = 49025 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 20617 ; free virtual = 49026 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 20615 ; free virtual = 49024 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 20650 ; free virtual = 49060 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 20635 ; free virtual = 49045 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 20632 ; free virtual = 49041 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 20628 ; free virtual = 49038 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20493 ; free virtual = 48904 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20456 ; free virtual = 48867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20448 ; free virtual = 48858 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20452 ; free virtual = 48862 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4961 --------------------------------------------------------------------------------- Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20408 ; free virtual = 48819 --------------------------------------------------------------------------------- 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 2532.703 ; gain = 339.105 ; free physical = 20408 ; free virtual = 48820 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:46 2019... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 21287 ; free virtual = 49699 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5016 Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 21148 ; free virtual = 49561 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21144 ; free virtual = 49559 --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21102 ; free virtual = 49517 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21123 ; free virtual = 49538 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21106 ; free virtual = 49521 --------------------------------------------------------------------------------- Loading site data... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000001 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 21106 ; free virtual = 49522 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 21083 ; free virtual = 49499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 21082 ; free virtual = 49498 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1205.957 ; gain = 110.508 ; free physical = 21046 ; free virtual = 49461 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] Creating bitstream... Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 20879 ; free virtual = 49297 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 20907 ; free virtual = 49328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 20910 ; free virtual = 49331 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 20935 ; free virtual = 49356 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 21019 ; free virtual = 49441 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20987 ; free virtual = 49409 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20987 ; free virtual = 49408 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 20995 ; free virtual = 49417 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 20994 ; free virtual = 49415 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20989 ; free virtual = 49410 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20950 ; free virtual = 49374 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20946 ; free virtual = 49371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20943 ; free virtual = 49369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20941 ; free virtual = 49368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20939 ; free virtual = 49366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20937 ; free virtual = 49364 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20934 ; free virtual = 49361 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20938 ; free virtual = 49361 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 20941 ; free virtual = 49363 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20883 ; free virtual = 49309 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20885 ; free virtual = 49310 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20887 ; free virtual = 49313 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20887 ; free virtual = 49314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20892 ; free virtual = 49318 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20894 ; free virtual = 49321 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20897 ; free virtual = 49324 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20904 ; free virtual = 49331 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20908 ; free virtual = 49334 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 20941 ; free virtual = 49367 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Loading data files... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 20980 ; free virtual = 49407 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21002 ; free virtual = 49428 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21102 ; free virtual = 49529 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21102 ; free virtual = 49529 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 21103 ; free virtual = 49530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21102 ; free virtual = 49529 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21100 ; free virtual = 49527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21100 ; free virtual = 49527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21100 ; free virtual = 49527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21099 ; free virtual = 49526 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21095 ; free virtual = 49522 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 21096 ; free virtual = 49523 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:54 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2451.875 ; gain = 343.105 ; free physical = 21049 ; free virtual = 49476 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:54 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:478] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:496] Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 21689 ; free virtual = 50118 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 21718 ; free virtual = 50148 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21667 ; free virtual = 50100 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 21673 ; free virtual = 50103 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1328.934 ; gain = 233.484 ; free physical = 21669 ; free virtual = 50108 --------------------------------------------------------------------------------- 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1396.688 ; gain = 313.797 ; free physical = 21682 ; free virtual = 50117 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 21686 ; free virtual = 50117 --------------------------------------------------------------------------------- Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1328.934 ; gain = 233.484 ; free physical = 21681 ; free virtual = 50111 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 21686 ; free virtual = 50116 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 21651 ; free virtual = 50081 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 21650 ; free virtual = 50081 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Device 21-403] Loading part xc7z020clg400-1 Starting Placer Task INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:56:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2452.867 ; gain = 344.105 ; free physical = 21656 ; free virtual = 50087 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:56:56 2019... INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 21665 ; free virtual = 50096 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 21665 ; free virtual = 50096 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21677 ; free virtual = 50107 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21698 ; free virtual = 50129 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1401.684 ; gain = 318.797 ; free physical = 21704 ; free virtual = 50134 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21708 ; free virtual = 50139 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21712 ; free virtual = 50143 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21714 ; free virtual = 50145 Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21715 ; free virtual = 50146 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21718 ; free virtual = 50148 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. INFO: [DRC 23-27] Running DRC with 8 threads Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21728 ; free virtual = 50158 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 21729 ; free virtual = 50159 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 21806 ; free virtual = 50237 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 22552 ; free virtual = 50984 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 22552 ; free virtual = 50983 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22546 ; free virtual = 50978 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22546 ; free virtual = 50977 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22543 ; free virtual = 50974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22543 ; free virtual = 50974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22541 ; free virtual = 50973 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22540 ; free virtual = 50971 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22539 ; free virtual = 50970 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.949 ; gain = 242.500 ; free physical = 22524 ; free virtual = 50955 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.957 ; gain = 242.500 ; free physical = 22522 ; free virtual = 50953 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2155] No constraint files found. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2267] --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1306.926 ; gain = 211.480 ; free physical = 22453 ; free virtual = 50885 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1306.926 ; gain = 211.480 ; free physical = 22445 ; free virtual = 50878 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22421 ; free virtual = 50857 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 22408 ; free virtual = 50840 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1397.680 ; gain = 314.789 ; free physical = 22416 ; free virtual = 50848 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 22374 ; free virtual = 50806 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 22370 ; free virtual = 50802 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.949 ; gain = 115.504 ; free physical = 22406 ; free virtual = 50839 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22252 ; free virtual = 50686 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22243 ; free virtual = 50677 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22237 ; free virtual = 50671 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22235 ; free virtual = 50669 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22230 ; free virtual = 50664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22227 ; free virtual = 50661 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22224 ; free virtual = 50659 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.902 ; gain = 219.457 ; free physical = 22215 ; free virtual = 50650 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.910 ; gain = 219.457 ; free physical = 22210 ; free virtual = 50645 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.711 ; gain = 0.000 ; free physical = 22252 ; free virtual = 50687 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1462.711 ; gain = 0.000 ; free physical = 22252 ; free virtual = 50686 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 21876 ; free virtual = 50313 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.949 ; gain = 338.055 ; free physical = 21885 ; free virtual = 50322 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 21794 ; free virtual = 50233 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 21798 ; free virtual = 50236 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.980 ; gain = 0.000 ; free physical = 21804 ; free virtual = 50242 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1484.980 ; gain = 0.000 ; free physical = 21804 ; free virtual = 50242 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 21746 ; free virtual = 50185 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 21703 ; free virtual = 50143 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21700 ; free virtual = 50139 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1405.926 ; gain = 323.039 ; free physical = 21705 ; free virtual = 50144 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21662 ; free virtual = 50102 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21660 ; free virtual = 50101 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21659 ; free virtual = 50100 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21659 ; free virtual = 50100 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21659 ; free virtual = 50100 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21659 ; free virtual = 50100 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21658 ; free virtual = 50099 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21656 ; free virtual = 50097 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 21658 ; free virtual = 50099 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1469.957 ; gain = 0.000 ; free physical = 21623 ; free virtual = 50064 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21623 ; free virtual = 50064 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1469.957 ; gain = 0.000 ; free physical = 21623 ; free virtual = 50065 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21582 ; free virtual = 50023 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21544 ; free virtual = 49986 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21401 ; free virtual = 49844 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21401 ; free virtual = 49843 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21477 ; free virtual = 49919 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21489 ; free virtual = 49931 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21499 ; free virtual = 49941 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21499 ; free virtual = 49941 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21498 ; free virtual = 49941 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21497 ; free virtual = 49940 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 21498 ; free virtual = 49940 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5438 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1416.699 ; gain = 333.812 ; free physical = 20831 ; free virtual = 49278 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing bitstream ./design.bit... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 20829 ; free virtual = 49278 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.207 ; gain = 0.000 ; free physical = 20678 ; free virtual = 49130 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Placer Task INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1813.203 ; gain = 0.000 ; free physical = 20654 ; free virtual = 49107 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.730 ; gain = 0.000 ; free physical = 20617 ; free virtual = 49069 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1482.730 ; gain = 0.000 ; free physical = 20642 ; free virtual = 49095 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20638 ; free virtual = 49090 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20634 ; free virtual = 49086 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20634 ; free virtual = 49086 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20634 ; free virtual = 49086 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20633 ; free virtual = 49086 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 20633 ; free virtual = 49085 Phase 1.3 Build Placer Netlist Model Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 20633 ; free virtual = 49085 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.250 ; gain = 507.562 ; free physical = 20633 ; free virtual = 49086 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 20620 ; free virtual = 49072 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 20619 ; free virtual = 49072 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 20619 ; free virtual = 49072 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 20618 ; free virtual = 49071 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 20618 ; free virtual = 49070 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 499.562 ; free physical = 20618 ; free virtual = 49070 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 20592 ; free virtual = 49044 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d7f8aeb2 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 20588 ; free virtual = 49040 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 20223 ; free virtual = 48677 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5629 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 20225 ; free virtual = 48679 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 20120 ; free virtual = 48574 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 20115 ; free virtual = 48570 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 20115 ; free virtual = 48570 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 20115 ; free virtual = 48569 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 20115 ; free virtual = 48569 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 20115 ; free virtual = 48570 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 20114 ; free virtual = 48568 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:57:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] write_bitstream completed successfully WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] write_bitstream: Time (s): cpu = 00:01:03 ; elapsed = 00:00:38 . Memory (MB): peak = 2608.445 ; gain = 390.160 ; free physical = 20114 ; free virtual = 48569 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:57:20 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5715 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.469 ; gain = 0.000 ; free physical = 20277 ; free virtual = 48745 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 20244 ; free virtual = 48708 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 20242 ; free virtual = 48706 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1939.512 ; gain = 454.531 ; free physical = 20210 ; free virtual = 48680 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1939.512 ; gain = 454.531 ; free physical = 20192 ; free virtual = 48662 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1939.512 ; gain = 454.531 ; free physical = 20189 ; free virtual = 48659 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1939.512 ; gain = 454.531 ; free physical = 20189 ; free virtual = 48659 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 20130 ; free virtual = 48594 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 20126 ; free virtual = 48590 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 20110 ; free virtual = 48574 Phase 1.3 Build Placer Netlist Model INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 20023 ; free virtual = 48488 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 19978 ; free virtual = 48443 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 19989 ; free virtual = 48454 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 19982 ; free virtual = 48447 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 19977 ; free virtual = 48442 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 19976 ; free virtual = 48441 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.445 ; gain = 0.000 ; free physical = 19906 ; free virtual = 48371 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 19852 ; free virtual = 48317 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 19839 ; free virtual = 48304 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 19838 ; free virtual = 48303 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 19839 ; free virtual = 48305 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 19841 ; free virtual = 48307 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 19844 ; free virtual = 48309 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 580.562 ; free physical = 19844 ; free virtual = 48309 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 19749 ; free virtual = 48215 --------------------------------------------------------------------------------- Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19599 ; free virtual = 48066 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19597 ; free virtual = 48065 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19581 ; free virtual = 48049 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1272.293 ; gain = 176.672 ; free physical = 19573 ; free virtual = 48040 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19564 ; free virtual = 48031 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19564 ; free virtual = 48031 Phase 3.5 Small Shape Detail Placement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19549 ; free virtual = 48017 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19549 ; free virtual = 48017 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19549 ; free virtual = 48017 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19549 ; free virtual = 48017 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19548 ; free virtual = 48016 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19547 ; free virtual = 48015 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19547 ; free virtual = 48015 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19547 ; free virtual = 48015 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19547 ; free virtual = 48015 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.559 ; gain = 550.578 ; free physical = 19558 ; free virtual = 48026 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2035.559 ; gain = 614.609 ; free physical = 19558 ; free virtual = 48026 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 19474 ; free virtual = 47943 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:16] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 19317 ; free virtual = 47788 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 19303 ; free virtual = 47780 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19260 ; free virtual = 47731 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19195 ; free virtual = 47673 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19166 ; free virtual = 47638 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 19147 ; free virtual = 47619 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18533 ; free virtual = 47006 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18528 ; free virtual = 47001 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.219 ; gain = 0.000 ; free physical = 18528 ; free virtual = 47001 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18517 ; free virtual = 46989 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18516 ; free virtual = 46989 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18513 ; free virtual = 46986 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18513 ; free virtual = 46986 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18513 ; free virtual = 46986 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [Timing 38-35] Done setting XDC timing constraints. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18509 ; free virtual = 46982 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.590 ; gain = 269.961 ; free physical = 18512 ; free virtual = 46985 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1907.453 ; gain = 0.000 ; free physical = 18498 ; free virtual = 46971 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.262 ; gain = 510.531 ; free physical = 18501 ; free virtual = 46974 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.262 ; gain = 510.531 ; free physical = 18509 ; free virtual = 46982 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.262 ; gain = 510.531 ; free physical = 18504 ; free virtual = 46977 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.262 ; gain = 510.531 ; free physical = 18503 ; free virtual = 46975 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.262 ; gain = 510.531 ; free physical = 18502 ; free virtual = 46975 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.262 ; gain = 510.531 ; free physical = 18503 ; free virtual = 46976 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.262 ; gain = 576.562 ; free physical = 18503 ; free virtual = 46976 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ddcd7ec8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 506.531 ; free physical = 18464 ; free virtual = 46938 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 506.531 ; free physical = 18459 ; free virtual = 46933 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 506.531 ; free physical = 18460 ; free virtual = 46933 Phase 1 Placer Initialization | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 506.531 ; free physical = 18459 ; free virtual = 46932 Phase 2 Global Placement WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:16] INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:7] WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1268.086 ; gain = 172.469 ; free physical = 18419 ; free virtual = 46893 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18398 ; free virtual = 46873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18319 ; free virtual = 46795 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 18319 ; free virtual = 46795 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 26d08ed71 Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18167 ; free virtual = 46644 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26d08ed71 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18161 ; free virtual = 46638 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 20d0b931e Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18153 ; free virtual = 46629 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1e6e670e9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18137 ; free virtual = 46613 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b09ad14e Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18133 ; free virtual = 46610 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18077 ; free virtual = 46554 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18076 ; free virtual = 46553 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18074 ; free virtual = 46551 Phase 3 Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18072 ; free virtual = 46549 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18065 ; free virtual = 46542 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18060 ; free virtual = 46537 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18059 ; free virtual = 46536 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18057 ; free virtual = 46533 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18055 ; free virtual = 46531 Ending Placer Task | Checksum: 1c94b2d26 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2083.539 ; gain = 594.574 ; free physical = 18068 ; free virtual = 46545 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2083.539 ; gain = 658.605 ; free physical = 18068 ; free virtual = 46544 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 18004 ; free virtual = 46482 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4ab841c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.680 ; gain = 249.062 ; free physical = 17947 ; free virtual = 46425 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.680 ; gain = 249.062 ; free physical = 17961 ; free virtual = 46439 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17930 ; free virtual = 46409 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17823 ; free virtual = 46302 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17819 ; free virtual = 46299 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17807 ; free virtual = 46286 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17806 ; free virtual = 46285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17802 ; free virtual = 46282 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17801 ; free virtual = 46280 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17799 ; free virtual = 46279 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 17796 ; free virtual = 46275 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.711 ; gain = 270.086 ; free physical = 17797 ; free virtual = 46277 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7641 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 1467.254 ; gain = 384.359 ; free physical = 17787 ; free virtual = 46271 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 17722 ; free virtual = 46204 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 17722 ; free virtual = 46203 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17744 ; free virtual = 46227 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Starting Placer Task --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1545.285 ; gain = 0.000 ; free physical = 17728 ; free virtual = 46211 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1545.285 ; gain = 0.000 ; free physical = 17722 ; free virtual = 46205 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17665 ; free virtual = 46149 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17660 ; free virtual = 46144 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17636 ; free virtual = 46120 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17636 ; free virtual = 46120 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17634 ; free virtual = 46118 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17633 ; free virtual = 46117 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17633 ; free virtual = 46117 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 17633 ; free virtual = 46117 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 17635 ; free virtual = 46118 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 17209 ; free virtual = 45698 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1 Build RT Design | Checksum: 109653c4d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2054.934 ; gain = 118.668 ; free physical = 17165 ; free virtual = 45654 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 109653c4d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2059.922 ; gain = 123.656 ; free physical = 17168 ; free virtual = 45657 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 109653c4d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2059.922 ; gain = 123.656 ; free physical = 17169 ; free virtual = 45658 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.375 ; gain = 384.484 ; free physical = 17169 ; free virtual = 45659 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17165 ; free virtual = 45654 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17104 ; free virtual = 45594 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] Phase 4 Rip-up And Reroute WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] Phase 4.1 Global Iteration 0 WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] Phase 4.1 Global Iteration 0 | Checksum: 116fd9d52 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17105 ; free virtual = 45594 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1224] Phase 4 Rip-up And Reroute | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17105 ; free virtual = 45594 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 116fd9d52 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1248] Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17105 ; free virtual = 45594 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1272] Phase 6.1 Hold Fix Iter | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17105 ; free virtual = 45594 Phase 6 Post Hold Fix | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17105 ; free virtual = 45594 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1632] Phase 7 Route finalize WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 17145 ; free virtual = 45635 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 17143 ; free virtual = 45633 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 17143 ; free virtual = 45633 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 17174 ; free virtual = 45664 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2108.766 ; gain = 204.516 ; free physical = 17174 ; free virtual = 45664 Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2054.930 ; gain = 121.668 ; free physical = 17174 ; free virtual = 45664 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2058.918 ; gain = 125.656 ; free physical = 17139 ; free virtual = 45629 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2058.918 ; gain = 125.656 ; free physical = 17139 ; free virtual = 45629 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 17127 ; free virtual = 45618 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17155 ; free virtual = 45645 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17111 ; free virtual = 45602 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 1.1 Placer Initialization Netlist Sorting Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17100 ; free virtual = 45591 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17100 ; free virtual = 45591 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17100 ; free virtual = 45591 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17100 ; free virtual = 45591 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17100 ; free virtual = 45591 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1545.078 ; gain = 0.000 ; free physical = 17100 ; free virtual = 45591 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17121 ; free virtual = 45611 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 135.711 ; free physical = 17121 ; free virtual = 45612 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 135.711 ; free physical = 17121 ; free virtual = 45612 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 135.711 ; free physical = 17155 ; free virtual = 45645 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2107.762 ; gain = 206.516 ; free physical = 17155 ; free virtual = 45646 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.50 . Memory (MB): peak = 1545.078 ; gain = 0.000 ; free physical = 17173 ; free virtual = 45664 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2107.762 ; gain = 0.000 ; free physical = 17172 ; free virtual = 45664 Running DRC as a precondition to command write_bitstream INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.254 ; gain = 384.367 ; free physical = 17201 ; free virtual = 45693 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2057.926 ; gain = 93.668 ; free physical = 17107 ; free virtual = 45599 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2063.914 ; gain = 99.656 ; free physical = 17070 ; free virtual = 45562 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2063.914 ; gain = 99.656 ; free physical = 17069 ; free virtual = 45562 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17067 ; free virtual = 45559 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17097 ; free virtual = 45589 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17091 ; free virtual = 45584 Phase 4 Rip-up And Reroute | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17090 ; free virtual = 45582 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17090 ; free virtual = 45582 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17090 ; free virtual = 45582 Phase 6 Post Hold Fix | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17090 ; free virtual = 45582 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 17074 ; free virtual = 45567 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.969 ; gain = 108.711 ; free physical = 17073 ; free virtual = 45566 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.969 ; gain = 108.711 ; free physical = 17070 ; free virtual = 45563 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.969 ; gain = 108.711 ; free physical = 17100 ; free virtual = 45593 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2111.758 ; gain = 179.516 ; free physical = 17099 ; free virtual = 45591 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.957 ; gain = 0.000 ; free physical = 17072 ; free virtual = 45565 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2111.758 ; gain = 0.000 ; free physical = 17020 ; free virtual = 45514 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1547.957 ; gain = 0.000 ; free physical = 16978 ; free virtual = 45472 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.176 ; gain = 41.668 ; free physical = 16233 ; free virtual = 44730 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.773 ; gain = 0.000 ; free physical = 16209 ; free virtual = 44706 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 16206 ; free virtual = 44703 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 16206 ; free virtual = 44703 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 16079 ; free virtual = 44577 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2062.172 ; gain = 43.668 ; free physical = 16038 ; free virtual = 44536 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.160 ; gain = 50.656 ; free physical = 15938 ; free virtual = 44436 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.160 ; gain = 50.656 ; free physical = 15934 ; free virtual = 44432 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 15903 ; free virtual = 44401 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 15895 ; free virtual = 44394 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 15894 ; free virtual = 44393 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 15893 ; free virtual = 44391 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 15891 ; free virtual = 44390 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 15894 ; free virtual = 44393 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 15883 ; free virtual = 44381 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 15881 ; free virtual = 44380 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 15890 ; free virtual = 44389 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.215 ; gain = 60.711 ; free physical = 15897 ; free virtual = 44396 Phase 3 Initial Routing INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 15938 ; free virtual = 44437 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2125.383 ; gain = 133.891 ; free physical = 15940 ; free virtual = 44439 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Writing placer database... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.488 ; gain = 458.203 ; free physical = 15996 ; free virtual = 44499 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Writing XDEF routing. Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15991 ; free virtual = 44495 Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15979 ; free virtual = 44485 Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2125.383 ; gain = 0.000 ; free physical = 15979 ; free virtual = 44485 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15979 ; free virtual = 44485 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15979 ; free virtual = 44485 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15979 ; free virtual = 44485 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15979 ; free virtual = 44485 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15975 ; free virtual = 44483 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.215 ; gain = 65.711 ; free physical = 15974 ; free virtual = 44483 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.215 ; gain = 65.711 ; free physical = 15966 ; free virtual = 44477 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.215 ; gain = 65.711 ; free physical = 16002 ; free virtual = 44513 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2123.004 ; gain = 136.516 ; free physical = 16001 ; free virtual = 44512 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2123.004 ; gain = 0.000 ; free physical = 15951 ; free virtual = 44472 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 15941 ; free virtual = 44443 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.199 ; gain = 34.641 ; free physical = 15930 ; free virtual = 44432 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2075.188 ; gain = 39.629 ; free physical = 15906 ; free virtual = 44409 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2075.188 ; gain = 39.629 ; free physical = 15906 ; free virtual = 44409 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15888 ; free virtual = 44411 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15818 ; free virtual = 44341 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15816 ; free virtual = 44339 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15816 ; free virtual = 44339 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15816 ; free virtual = 44339 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15816 ; free virtual = 44339 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15816 ; free virtual = 44339 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15787 ; free virtual = 44310 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15787 ; free virtual = 44310 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15784 ; free virtual = 44307 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.242 ; gain = 61.684 ; free physical = 15814 ; free virtual = 44337 Routing Is Done. 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.031 ; gain = 100.473 ; free physical = 15809 ; free virtual = 44332 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing placer database... Writing XDEF routing. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 15824 ; free virtual = 44328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 15824 ; free virtual = 44328 --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2136.031 ; gain = 0.000 ; free physical = 15823 ; free virtual = 44328 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading site data... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.488 ; gain = 458.203 ; free physical = 15668 ; free virtual = 44172 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.488 ; gain = 458.203 ; free physical = 15703 ; free virtual = 44207 Loading route data... Processing options... Creating bitmap... Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.488 ; gain = 458.203 ; free physical = 15660 ; free virtual = 44165 Phase 2 Global Placement Running DRC as a precondition to command write_bitstream Loading site data... Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading data files... Phase 1 Build RT Design | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.945 ; gain = 42.668 ; free physical = 15144 ; free virtual = 43651 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.934 ; gain = 48.656 ; free physical = 15073 ; free virtual = 43580 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.934 ; gain = 48.656 ; free physical = 15058 ; free virtual = 43565 Loading site data... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14792 ; free virtual = 43300 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.238 ; gain = 60.961 ; free physical = 14777 ; free virtual = 43284 Phase 3 Initial Routing Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14789 ; free virtual = 43301 Phase 3.2 Commit Most Macros & LUTRAMs Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.238 ; gain = 63.961 ; free physical = 14793 ; free virtual = 43305 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.238 ; gain = 63.961 ; free physical = 14832 ; free virtual = 43344 Phase 4 Rip-up And Reroute | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.238 ; gain = 63.961 ; free physical = 14844 ; free virtual = 43356 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.238 ; gain = 63.961 ; free physical = 14841 ; free virtual = 43353 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.238 ; gain = 63.961 ; free physical = 14851 ; free virtual = 43363 Phase 6 Post Hold Fix | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.238 ; gain = 63.961 ; free physical = 14868 ; free virtual = 43380 Phase 7 Route finalize INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 15047 ; free virtual = 43559 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 7 Route finalize | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.238 ; gain = 63.961 ; free physical = 15044 ; free virtual = 43556 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.238 ; gain = 65.961 ; free physical = 15038 ; free virtual = 43550 Phase 9 Depositing Routes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.566 ; gain = 0.000 ; free physical = 15023 ; free virtual = 43535 Phase 9 Depositing Routes | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.238 ; gain = 65.961 ; free physical = 14983 ; free virtual = 43495 INFO: [Route 35-16] Router Completed Successfully Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.238 ; gain = 65.961 ; free physical = 15020 ; free virtual = 43533 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2130.027 ; gain = 136.766 ; free physical = 15016 ; free virtual = 43528 Writing bitstream ./design.bit... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14932 ; free virtual = 43446 Writing placer database... Phase 3.3 Area Swap Optimization Loading data files... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 15082 ; free virtual = 43602 Phase 3.4 Pipeline Register Optimization Write XDEF Complete: Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2130.027 ; gain = 0.000 ; free physical = 15090 ; free virtual = 43611 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 15244 ; free virtual = 43764 Phase 3.5 Small Shape Detail Placement INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.281 ; gain = 458.203 ; free physical = 14953 ; free virtual = 43471 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14884 ; free virtual = 43403 Phase 3.6 Re-assign LUT pins INFO: [Timing 38-35] Done setting XDC timing constraints. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14845 ; free virtual = 43364 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14826 ; free virtual = 43344 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14818 ; free virtual = 43336 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 14812 ; free virtual = 43331 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14797 ; free virtual = 43316 Phase 4.2 Post Placement Cleanup --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 14789 ; free virtual = 43308 --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14789 ; free virtual = 43308 Phase 4.3 Placer Reporting Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14770 ; free virtual = 43290 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 14770 ; free virtual = 43290 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:58:27 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.871 ; gain = 341.105 ; free physical = 14747 ; free virtual = 43268 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14747 ; free virtual = 43268 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:58:27 2019... Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 14865 ; free virtual = 43388 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:58:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1 Build RT Design | Checksum: 13eb18239 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2083.539 ; gain = 0.000 ; free physical = 15999 ; free virtual = 44523 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.535 ; gain = 554.250 ; free physical = 16005 ; free virtual = 44528 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.535 ; gain = 632.281 ; free physical = 16017 ; free virtual = 44540 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2450.867 ; gain = 343.105 ; free physical = 16024 ; free virtual = 44547 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:58:28 2019... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13eb18239 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2083.539 ; gain = 0.000 ; free physical = 16060 ; free virtual = 44583 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13eb18239 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2083.539 ; gain = 0.000 ; free physical = 16060 ; free virtual = 44584 Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 30 #of tags: 3 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 16778 ; free virtual = 45301 Phase 1.3 Build Placer Netlist Model Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12e953610 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16785 ; free virtual = 45309 Phase 3 Initial Routing touch build/specimen_002/OK Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.281 ; gain = 458.203 ; free physical = 16814 ; free virtual = 45338 Phase 1.4 Constrain Clocks/Macros GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16812 ; free virtual = 45336 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.281 ; gain = 458.203 ; free physical = 16819 ; free virtual = 45344 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16818 ; free virtual = 45342 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16818 ; free virtual = 45342 Phase 4 Rip-up And Reroute | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16820 ; free virtual = 45345 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16818 ; free virtual = 45343 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16816 ; free virtual = 45340 Phase 6 Post Hold Fix | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16815 ; free virtual = 45340 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16755 ; free virtual = 45279 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16746 ; free virtual = 45270 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16724 ; free virtual = 45248 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.281 ; gain = 458.203 ; free physical = 16732 ; free virtual = 45256 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 17.688 ; free physical = 16763 ; free virtual = 45287 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2140.016 ; gain = 56.477 ; free physical = 16764 ; free virtual = 45288 Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 16811 ; free virtual = 45343 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading data files... Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16665 ; free virtual = 45196 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading route data... Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16689 ; free virtual = 45220 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16654 ; free virtual = 45185 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16640 ; free virtual = 45171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16631 ; free virtual = 45162 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16629 ; free virtual = 45160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16628 ; free virtual = 45159 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 16626 ; free virtual = 45157 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 16626 ; free virtual = 45157 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:58:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2454.863 ; gain = 343.105 ; free physical = 16551 ; free virtual = 45082 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:58:31 2019... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 17447 ; free virtual = 45978 Phase 1.4 Constrain Clocks/Macros touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17430 ; free virtual = 45962 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 17401 ; free virtual = 45933 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17369 ; free virtual = 45901 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 17280 ; free virtual = 45813 Phase 2 Global Placement Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17348 ; free virtual = 45881 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17390 ; free virtual = 45922 Phase 3.4 Pipeline Register Optimization Loading site data... Creating bitstream... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17325 ; free virtual = 45857 Phase 3.5 Small Shape Detail Placement Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Creating bitstream... Loading data files... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17209 ; free virtual = 45743 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17200 ; free virtual = 45734 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17188 ; free virtual = 45722 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17180 ; free virtual = 45715 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17179 ; free virtual = 45714 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Writing bitstream ./design.bit... Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17167 ; free virtual = 45702 Phase 3.2 Commit Most Macros & LUTRAMs Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17162 ; free virtual = 45697 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17132 ; free virtual = 45671 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17258 ; free virtual = 45797 Phase 4.4 Final Placement Cleanup Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17259 ; free virtual = 45798 Phase 3.3 Area Swap Optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17369 ; free virtual = 45908 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17356 ; free virtual = 45895 Phase 3.4 Pipeline Register Optimization Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17341 ; free virtual = 45880 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17361 ; free virtual = 45900 Phase 3.5 Small Shape Detail Placement Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 546.246 ; free physical = 17336 ; free virtual = 45876 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.324 ; gain = 623.949 ; free physical = 17336 ; free virtual = 45875 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Writing bitstream ./design.bit... INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17542 ; free virtual = 46086 Phase 3.6 Re-assign LUT pins Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17517 ; free virtual = 46062 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17486 ; free virtual = 46030 Loading site data... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17474 ; free virtual = 46019 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17456 ; free virtual = 46002 Phase 4.2 Post Placement Cleanup Loading route data... Writing bitstream ./design.bit... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:58:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2470.488 ; gain = 345.105 ; free physical = 17423 ; free virtual = 45971 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:58:42 2019... Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17423 ; free virtual = 45972 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 17679 ; free virtual = 46228 Phase 4.4 Final Placement Cleanup INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 18664 ; free virtual = 47213 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 18659 ; free virtual = 47208 touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.203 ; gain = 543.246 ; free physical = 18598 ; free virtual = 47148 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.203 ; gain = 623.949 ; free physical = 18595 ; free virtual = 47145 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:58:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2467.137 ; gain = 331.105 ; free physical = 18472 ; free virtual = 47023 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:58:44 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. #of segments: 2 #of bits: 388 #of tags: 1 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:58:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2462.109 ; gain = 339.105 ; free physical = 19505 ; free virtual = 48056 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:58:46 2019... Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11029 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11070 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11109 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:11 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 20326 ; free virtual = 48892 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:58:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2470.133 ; gain = 340.105 ; free physical = 20365 ; free virtual = 48931 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:58:58 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 21204 ; free virtual = 49774 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 21146 ; free virtual = 49716 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:59:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.121 ; gain = 335.105 ; free physical = 21175 ; free virtual = 49745 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:59:01 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 21966 ; free virtual = 50540 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 21833 ; free virtual = 50408 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 21840 ; free virtual = 50415 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 21831 ; free virtual = 50407 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 21830 ; free virtual = 50405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 21829 ; free virtual = 50405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 21822 ; free virtual = 50398 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11322 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11358 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 21624 ; free virtual = 50201 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 21614 ; free virtual = 50192 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 21612 ; free virtual = 50190 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 21594 ; free virtual = 50171 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11426 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2130.293 ; gain = 30.758 ; free physical = 21254 ; free virtual = 49835 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.281 ; gain = 36.746 ; free physical = 21185 ; free virtual = 49766 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.281 ; gain = 36.746 ; free physical = 21185 ; free virtual = 49765 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21181 ; free virtual = 49762 Phase 3 Initial Routing No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 21172 ; free virtual = 49753 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 21150 ; free virtual = 49731 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21137 ; free virtual = 49717 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21037 ; free virtual = 49618 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21033 ; free virtual = 49614 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21033 ; free virtual = 49614 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21033 ; free virtual = 49614 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21033 ; free virtual = 49614 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21033 ; free virtual = 49613 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21107 ; free virtual = 49688 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21105 ; free virtual = 49686 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21103 ; free virtual = 49684 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.336 ; gain = 54.801 ; free physical = 21136 ; free virtual = 49717 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2193.125 ; gain = 93.590 ; free physical = 21136 ; free virtual = 49717 Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21089 ; free virtual = 49674 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21088 ; free virtual = 49673 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21088 ; free virtual = 49672 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21087 ; free virtual = 49672 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21087 ; free virtual = 49672 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21087 ; free virtual = 49672 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21086 ; free virtual = 49671 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21086 ; free virtual = 49671 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 21086 ; free virtual = 49672 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 21007 ; free virtual = 49596 --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 20901 ; free virtual = 49496 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 20899 ; free virtual = 49495 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20892 ; free virtual = 49488 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20888 ; free virtual = 49485 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] Writing XDEF routing. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20769 ; free virtual = 49375 --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.125 ; gain = 0.000 ; free physical = 20765 ; free virtual = 49372 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20757 ; free virtual = 49363 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20752 ; free virtual = 49358 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20748 ; free virtual = 49354 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20744 ; free virtual = 49350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20740 ; free virtual = 49346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20737 ; free virtual = 49343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20733 ; free virtual = 49339 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20723 ; free virtual = 49329 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.676 ; gain = 216.219 ; free physical = 20721 ; free virtual = 49327 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20679 ; free virtual = 49285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20671 ; free virtual = 49277 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20588 ; free virtual = 49195 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20440 ; free virtual = 49025 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20390 ; free virtual = 48976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20391 ; free virtual = 48977 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20420 ; free virtual = 49006 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 20299 ; free virtual = 48906 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 20296 ; free virtual = 48904 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 20317 ; free virtual = 48905 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1401.684 ; gain = 318.797 ; free physical = 20323 ; free virtual = 48911 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 20388 ; free virtual = 48996 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 20387 ; free virtual = 48995 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2129.555 ; gain = 38.230 ; free physical = 20250 ; free virtual = 48859 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2135.543 ; gain = 44.219 ; free physical = 20186 ; free virtual = 48795 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2135.543 ; gain = 44.219 ; free physical = 20187 ; free virtual = 48796 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 20184 ; free virtual = 48773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 20183 ; free virtual = 48772 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20141 ; free virtual = 48730 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 20130 ; free virtual = 48724 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 20141 ; free virtual = 48730 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11556 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1398.691 ; gain = 315.797 ; free physical = 20146 ; free virtual = 48736 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 20159 ; free virtual = 48749 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 20159 ; free virtual = 48749 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20156 ; free virtual = 48746 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 20163 ; free virtual = 48753 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20163 ; free virtual = 48753 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20163 ; free virtual = 48753 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20163 ; free virtual = 48753 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20163 ; free virtual = 48753 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20163 ; free virtual = 48753 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20178 ; free virtual = 48768 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20175 ; free virtual = 48765 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20172 ; free virtual = 48762 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.598 ; gain = 63.273 ; free physical = 20205 ; free virtual = 48795 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:42 . Memory (MB): peak = 2193.387 ; gain = 102.062 ; free physical = 20202 ; free virtual = 48792 Writing placer database... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11618 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 19961 ; free virtual = 48558 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 19959 ; free virtual = 48556 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.387 ; gain = 0.000 ; free physical = 19700 ; free virtual = 48316 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19698 ; free virtual = 48314 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19694 ; free virtual = 48310 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 19687 ; free virtual = 48304 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19686 ; free virtual = 48302 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:29 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 19697 ; free virtual = 48314 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 19696 ; free virtual = 48312 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2129.434 ; gain = 38.230 ; free physical = 19681 ; free virtual = 48279 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 19679 ; free virtual = 48279 Phase 2 Final Placement Cleanup Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2136.422 ; gain = 45.219 ; free physical = 19643 ; free virtual = 48237 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2136.422 ; gain = 45.219 ; free physical = 19643 ; free virtual = 48237 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 19616 ; free virtual = 48210 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19596 ; free virtual = 48190 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19572 ; free virtual = 48167 Ending Placer Task | Checksum: 110ed1b10 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 19570 ; free virtual = 48165 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 19568 ; free virtual = 48163 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19576 ; free virtual = 48170 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19553 ; free virtual = 48148 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19554 ; free virtual = 48148 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19564 ; free virtual = 48159 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19564 ; free virtual = 48159 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19564 ; free virtual = 48159 --------------------------------------------------------------------------------- Phase 3 Initial Routing --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19563 ; free virtual = 48157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19563 ; free virtual = 48157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19562 ; free virtual = 48157 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19563 ; free virtual = 48158 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 19590 ; free virtual = 48185 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19560 ; free virtual = 48155 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19538 ; free virtual = 48133 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19538 ; free virtual = 48133 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19538 ; free virtual = 48133 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19538 ; free virtual = 48133 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19538 ; free virtual = 48133 Running DRC as a precondition to command write_bitstream Phase 7 Route finalize Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19513 ; free virtual = 48109 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19513 ; free virtual = 48109 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19511 ; free virtual = 48107 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.477 ; gain = 64.273 ; free physical = 19543 ; free virtual = 48138 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:44 . Memory (MB): peak = 2194.266 ; gain = 103.062 ; free physical = 19542 ; free virtual = 48138 Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19468 ; free virtual = 48065 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19466 ; free virtual = 48063 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19463 ; free virtual = 48061 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19463 ; free virtual = 48061 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19464 ; free virtual = 48062 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19464 ; free virtual = 48062 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19464 ; free virtual = 48061 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19463 ; free virtual = 48060 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 19464 ; free virtual = 48062 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 19320 ; free virtual = 47931 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 19264 ; free virtual = 47877 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 19262 ; free virtual = 47876 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 19205 ; free virtual = 47821 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19214 ; free virtual = 47830 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 19244 ; free virtual = 47862 --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.266 ; gain = 0.000 ; free physical = 19176 ; free virtual = 47798 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 19164 ; free virtual = 47785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19126 ; free virtual = 47748 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19124 ; free virtual = 47746 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19120 ; free virtual = 47742 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19119 ; free virtual = 47741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19118 ; free virtual = 47740 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 19117 ; free virtual = 47740 Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19117 ; free virtual = 47739 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19115 ; free virtual = 47738 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 19112 ; free virtual = 47735 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 19108 ; free virtual = 47731 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4314] Loading data files... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5725] INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1287] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18844 ; free virtual = 47446 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:16] Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18843 ; free virtual = 47445 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 18840 ; free virtual = 47442 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18838 ; free virtual = 47440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18839 ; free virtual = 47446 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 18840 ; free virtual = 47442 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18837 ; free virtual = 47440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18824 ; free virtual = 47427 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18819 ; free virtual = 47421 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1417] Synthesis Optimization Runtime : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18807 ; free virtual = 47410 WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18807 ; free virtual = 47410 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] INFO: [Project 1-571] Translating synthesized netlist 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 18828 ; free virtual = 47435 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 18848 ; free virtual = 47451 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 18860 ; free virtual = 47463 --------------------------------------------------------------------------------- Loading site data... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 18881 ; free virtual = 47485 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 18877 ; free virtual = 47481 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 18800 ; free virtual = 47404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18803 ; free virtual = 47407 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 18781 ; free virtual = 47386 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 18810 ; free virtual = 47414 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 18785 ; free virtual = 47390 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 18778 ; free virtual = 47383 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18778 ; free virtual = 47383 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1405.926 ; gain = 323.039 ; free physical = 18279 ; free virtual = 46887 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.203 ; gain = 0.000 ; free physical = 17947 ; free virtual = 46555 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1469.957 ; gain = 0.000 ; free physical = 17929 ; free virtual = 46539 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1469.957 ; gain = 0.000 ; free physical = 17919 ; free virtual = 46530 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 17909 ; free virtual = 46521 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 17908 ; free virtual = 46521 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 17908 ; free virtual = 46520 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 17907 ; free virtual = 46520 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 17907 ; free virtual = 46520 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 17909 ; free virtual = 46522 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 499.562 ; free physical = 17909 ; free virtual = 46522 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1842.211 ; gain = 0.000 ; free physical = 17635 ; free virtual = 46250 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 17597 ; free virtual = 46212 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 17559 ; free virtual = 46174 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17553 ; free virtual = 46168 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 17520 ; free virtual = 46135 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:59:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2532.730 ; gain = 339.605 ; free physical = 17501 ; free virtual = 46116 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:59:43 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 17499 ; free virtual = 46114 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 17498 ; free virtual = 46113 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 17486 ; free virtual = 46101 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 17494 ; free virtual = 46108 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 17500 ; free virtual = 46115 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 17502 ; free virtual = 46116 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 17505 ; free virtual = 46120 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.254 ; gain = 531.562 ; free physical = 17505 ; free virtual = 46120 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... Processing options... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Creating bitmap... Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 17520 ; free virtual = 46135 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18442 ; free virtual = 47057 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18444 ; free virtual = 47059 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18440 ; free virtual = 47056 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18440 ; free virtual = 47056 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18443 ; free virtual = 47058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18443 ; free virtual = 47058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18443 ; free virtual = 47058 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18440 ; free virtual = 47055 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 18442 ; free virtual = 47058 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18362 ; free virtual = 46979 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18359 ; free virtual = 46976 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18359 ; free virtual = 46975 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18356 ; free virtual = 46973 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18356 ; free virtual = 46972 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18353 ; free virtual = 46970 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18353 ; free virtual = 46970 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 18350 ; free virtual = 46966 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 18351 ; free virtual = 46967 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement Creating bitstream... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 18194 ; free virtual = 46819 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 18229 ; free virtual = 46853 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 02:59:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.453 ; gain = 339.066 ; free physical = 18104 ; free virtual = 46729 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 02:59:53 2019... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 18100 ; free virtual = 46725 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1296e3a58 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 18103 ; free virtual = 46728 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 18136 ; free virtual = 46762 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 18144 ; free virtual = 46770 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 Writing bitstream ./design.bit... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 18667 ; free virtual = 47298 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18831 ; free virtual = 47462 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 18835 ; free virtual = 47467 Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18834 ; free virtual = 47465 Phase 1.4 Constrain Clocks/Macros Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18819 ; free virtual = 47450 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18804 ; free virtual = 47435 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18828 ; free virtual = 47460 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18830 ; free virtual = 47461 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 18829 ; free virtual = 47460 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18818 ; free virtual = 47450 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18809 ; free virtual = 47441 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18812 ; free virtual = 47444 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18812 ; free virtual = 47444 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18807 ; free virtual = 47439 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18810 ; free virtual = 47442 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 18809 ; free virtual = 47441 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:04 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 18749 ; free virtual = 47381 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.445 ; gain = 0.000 ; free physical = 18342 ; free virtual = 46976 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1557.855 ; gain = 0.000 ; free physical = 18323 ; free virtual = 46957 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 18323 ; free virtual = 46956 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:00:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 18324 ; free virtual = 46958 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 18326 ; free virtual = 46960 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.371 ; gain = 338.105 ; free physical = 18333 ; free virtual = 46967 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 18334 ; free virtual = 46967 Phase 2 Final Placement Cleanup INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:00:01 2019... Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 18336 ; free virtual = 46970 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1557.855 ; gain = 0.000 ; free physical = 18338 ; free virtual = 46972 Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 516.531 ; free physical = 18339 ; free virtual = 46972 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.488 ; gain = 580.562 ; free physical = 18338 ; free virtual = 46972 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12362 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 18333 ; free virtual = 46975 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 107963fbc Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2132.074 ; gain = 47.668 ; free physical = 18179 ; free virtual = 46822 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e1594fd1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18065 ; free virtual = 46708 Phase 1.3 Build Placer Netlist Model Phase 2.1 Fix Topology Constraints | Checksum: 107963fbc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2142.062 ; gain = 57.656 ; free physical = 18062 ; free virtual = 46705 Phase 2.2 Pre Route Cleanup Phase 1.3 Build Placer Netlist Model | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18061 ; free virtual = 46704 Phase 1.4 Constrain Clocks/Macros Phase 2.2 Pre Route Cleanup | Checksum: 107963fbc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2142.062 ; gain = 57.656 ; free physical = 18060 ; free virtual = 46703 Phase 1.4 Constrain Clocks/Macros | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18053 ; free virtual = 46697 Phase 1 Placer Initialization | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18053 ; free virtual = 46696 Phase 2 Global Placement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 18057 ; free virtual = 46700 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 18015 ; free virtual = 46658 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 18012 ; free virtual = 46655 Phase 1.4 Constrain Clocks/Macros Number of Nodes with overlaps = 0 Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 18012 ; free virtual = 46656 Phase 2 Router Initialization | Checksum: 1c2f462cb Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 18014 ; free virtual = 46657 Phase 3 Initial Routing Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 18012 ; free virtual = 46656 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 18005 ; free virtual = 46649 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 18003 ; free virtual = 46647 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 18003 ; free virtual = 46647 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17963 ; free virtual = 46607 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17941 ; free virtual = 46585 Phase 4 Rip-up And Reroute | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17936 ; free virtual = 46581 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17939 ; free virtual = 46584 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17941 ; free virtual = 46586 Phase 6 Post Hold Fix | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17939 ; free virtual = 46583 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17902 ; free virtual = 46546 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17873 ; free virtual = 46517 Phase 9 Depositing Routes WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 9 Depositing Routes | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17822 ; free virtual = 46469 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 17867 ; free virtual = 46512 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2217.281 ; gain = 164.891 ; free physical = 17868 ; free virtual = 46513 Writing placer database... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17782 ; free virtual = 46435 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17776 ; free virtual = 46428 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 215570181 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17767 ; free virtual = 46421 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ef31df4c Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17728 ; free virtual = 46382 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b8e63fb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17710 ; free virtual = 46365 Phase 3.5 Small Shape Detail Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.5 Small Shape Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17691 ; free virtual = 46349 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17694 ; free virtual = 46353 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17692 ; free virtual = 46351 Phase 3 Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17691 ; free virtual = 46350 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17687 ; free virtual = 46347 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17682 ; free virtual = 46342 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17680 ; free virtual = 46340 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17678 ; free virtual = 46339 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17671 ; free virtual = 46331 Ending Placer Task | Checksum: 146bf3d33 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17665 ; free virtual = 46326 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 659.605 ; free physical = 17663 ; free virtual = 46324 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13194 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 17640 ; free virtual = 46304 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.281 ; gain = 0.000 ; free physical = 17363 ; free virtual = 46040 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 621f9429 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:111] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:923] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1963.344 ; gain = 0.000 ; free physical = 17388 ; free virtual = 46073 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 17420 ; free virtual = 46073 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 17419 ; free virtual = 46072 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 17415 ; free virtual = 46068 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 17376 ; free virtual = 46029 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2051.387 ; gain = 493.531 ; free physical = 17289 ; free virtual = 45943 Phase 1.3 Build Placer Netlist Model Phase 1 Build RT Design | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2054.930 ; gain = 121.668 ; free physical = 17244 ; free virtual = 45898 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2059.918 ; gain = 126.656 ; free physical = 17221 ; free virtual = 45875 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2059.918 ; gain = 126.656 ; free physical = 17221 ; free virtual = 45875 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17203 ; free virtual = 45857 Phase 3 Initial Routing ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17178 ; free virtual = 45833 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17174 ; free virtual = 45828 Phase 4 Rip-up And Reroute | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17173 ; free virtual = 45828 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17173 ; free virtual = 45827 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17173 ; free virtual = 45827 Phase 6 Post Hold Fix | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17173 ; free virtual = 45827 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 17161 ; free virtual = 45816 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 134.711 ; free physical = 17159 ; free virtual = 45814 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 134.711 ; free physical = 17159 ; free virtual = 45814 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 134.711 ; free physical = 17193 ; free virtual = 45848 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2106.762 ; gain = 205.516 ; free physical = 17193 ; free virtual = 45848 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2106.762 ; gain = 0.000 ; free physical = 17175 ; free virtual = 45831 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13307 Phase 1 Build RT Design | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2055.938 ; gain = 93.668 ; free physical = 16948 ; free virtual = 45605 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.926 ; gain = 99.656 ; free physical = 16914 ; free virtual = 45570 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.926 ; gain = 99.656 ; free physical = 16914 ; free virtual = 45570 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 927a5c4b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16886 ; free virtual = 45543 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 16855 ; free virtual = 45511 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.387 ; gain = 493.531 ; free physical = 16804 ; free virtual = 45461 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16801 ; free virtual = 45459 Phase 1.4 Constrain Clocks/Macros Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16810 ; free virtual = 45468 Phase 4 Rip-up And Reroute | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16811 ; free virtual = 45468 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16812 ; free virtual = 45469 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16814 ; free virtual = 45471 Phase 6 Post Hold Fix | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16815 ; free virtual = 45472 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. Phase 7 Route finalize WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 927a5c4b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 16816 ; free virtual = 45473 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 927a5c4b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.980 ; gain = 109.711 ; free physical = 16816 ; free virtual = 45474 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 927a5c4b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.980 ; gain = 109.711 ; free physical = 16823 ; free virtual = 45480 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2071.980 ; gain = 109.711 ; free physical = 16855 ; free virtual = 45512 Routing Is Done. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.770 ; gain = 180.516 ; free physical = 16856 ; free virtual = 45513 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.387 ; gain = 493.531 ; free physical = 16857 ; free virtual = 45514 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.387 ; gain = 493.531 ; free physical = 16867 ; free virtual = 45526 Phase 2 Final Placement Cleanup Writing placer database... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 16846 ; free virtual = 45505 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.387 ; gain = 493.531 ; free physical = 16810 ; free virtual = 45468 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 16775 ; free virtual = 45433 --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.387 ; gain = 493.531 ; free physical = 16758 ; free virtual = 45416 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2051.387 ; gain = 574.562 ; free physical = 16751 ; free virtual = 45409 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 16684 ; free virtual = 45342 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16658 ; free virtual = 45316 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:475] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Running DRC as a precondition to command write_bitstream INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 16676 ; free virtual = 45335 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 16654 ; free virtual = 45313 Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16654 ; free virtual = 45313 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | --------------------------------------------------------------------------------- +------+------------------+-------+---------+-------+------------------+ Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16660 ; free virtual = 45319 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16660 ; free virtual = 45320 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 16660 ; free virtual = 45320 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16660 ; free virtual = 45320 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16656 ; free virtual = 45316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16656 ; free virtual = 45316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16656 ; free virtual = 45315 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. INFO: [Device 21-403] Loading part xc7z020clg400-1 Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16655 ; free virtual = 45314 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 16656 ; free virtual = 45315 Loading data files... INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 16624 ; free virtual = 45283 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 16168 ; free virtual = 44830 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 15934 ; free virtual = 44598 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 15782 ; free virtual = 44447 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e39310c0 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 15774 ; free virtual = 44439 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 15741 ; free virtual = 44406 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 15713 ; free virtual = 44379 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15696 ; free virtual = 44361 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.176 ; gain = 42.668 ; free physical = 15587 ; free virtual = 44252 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15586 ; free virtual = 44252 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15577 ; free virtual = 44242 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2066.176 ; gain = 42.668 ; free physical = 15576 ; free virtual = 44242 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15576 ; free virtual = 44241 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15573 ; free virtual = 44238 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15565 ; free virtual = 44230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15555 ; free virtual = 44221 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15541 ; free virtual = 44206 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 15532 ; free virtual = 44198 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 15536 ; free virtual = 44202 Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15517 ; free virtual = 44182 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 15513 ; free virtual = 44179 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 15510 ; free virtual = 44176 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 15509 ; free virtual = 44175 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:16] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.469 ; gain = 59.961 ; free physical = 15444 ; free virtual = 44110 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15440 ; free virtual = 44106 Phase 3 Initial Routing WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:7] Creating bitstream... Number of Nodes with overlaps = 0 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15420 ; free virtual = 44086 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15420 ; free virtual = 44087 Number of Nodes with overlaps = 0 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15420 ; free virtual = 44087 Phase 5 Delay and Skew Optimization Phase 3 Initial Routing | Checksum: 5700a6dd Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 15423 ; free virtual = 44090 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15423 ; free virtual = 44090 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15425 ; free virtual = 44092 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15425 ; free virtual = 44092 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 7 Route finalize Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 15435 ; free virtual = 44101 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 15436 ; free virtual = 44103 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 15438 ; free virtual = 44105 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 15441 ; free virtual = 44108 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 15443 ; free virtual = 44110 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 15467 ; free virtual = 44134 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 15465 ; free virtual = 44132 Phase 9 Depositing Routes Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 15453 ; free virtual = 44123 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 15452 ; free virtual = 44122 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 15451 ; free virtual = 44122 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 15489 ; free virtual = 44160 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2126.258 ; gain = 134.766 ; free physical = 15488 ; free virtual = 44160 Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 15484 ; free virtual = 44157 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 15521 ; free virtual = 44194 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 15521 ; free virtual = 44194 Writing placer database... Writing placer database... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 15521 ; free virtual = 44189 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Writing XDEF routing. Write XDEF Complete: Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2126.258 ; gain = 0.000 ; free physical = 15524 ; free virtual = 44197 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 15526 ; free virtual = 44201 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 15482 ; free virtual = 44151 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 15479 ; free virtual = 44149 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... Loading site data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 15333 ; free virtual = 44009 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2063.172 ; gain = 44.668 ; free physical = 15319 ; free virtual = 43995 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.160 ; gain = 49.656 ; free physical = 15290 ; free virtual = 43967 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.160 ; gain = 49.656 ; free physical = 15289 ; free virtual = 43966 Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2078.215 ; gain = 59.711 ; free physical = 15240 ; free virtual = 43918 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 15212 ; free virtual = 43890 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 15188 ; free virtual = 43866 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 15189 ; free virtual = 43867 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 15191 ; free virtual = 43869 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 15193 ; free virtual = 43870 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 15194 ; free virtual = 43872 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 15221 ; free virtual = 43898 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 15211 ; free virtual = 43889 Phase 8 Verifying routed nets Verification completed successfully INFO: [DRC 23-27] Running DRC with 8 threads Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15211 ; free virtual = 43889 Phase 9 Depositing Routes report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:00:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15194 ; free virtual = 43872 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 2450.867 ; gain = 344.105 ; free physical = 15203 ; free virtual = 43881 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:00:50 2019... INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 15226 ; free virtual = 43904 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2121.004 ; gain = 134.516 ; free physical = 15227 ; free virtual = 43905 Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2121.004 ; gain = 0.000 ; free physical = 15334 ; free virtual = 44015 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading data files... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 16115 ; free virtual = 44794 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a69706bf Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 16124 ; free virtual = 44803 Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 16202 ; free virtual = 44888 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 16204 ; free virtual = 44891 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16131 ; free virtual = 44818 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16044 ; free virtual = 44732 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16035 ; free virtual = 44723 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16036 ; free virtual = 44724 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16045 ; free virtual = 44733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16047 ; free virtual = 44735 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16039 ; free virtual = 44727 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16038 ; free virtual = 44726 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 16038 ; free virtual = 44726 Loading data files... Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 16040 ; free virtual = 44728 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:00:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2455.875 ; gain = 345.105 ; free physical = 16014 ; free virtual = 44703 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:00:58 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.957 ; gain = 42.668 ; free physical = 16786 ; free virtual = 45480 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.945 ; gain = 48.656 ; free physical = 16731 ; free virtual = 45426 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.945 ; gain = 48.656 ; free physical = 16729 ; free virtual = 45424 INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1aab43f05 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 16591 ; free virtual = 45287 Phase 3 Initial Routing Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 16584 ; free virtual = 45280 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 16526 ; free virtual = 45222 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 16522 ; free virtual = 45218 Phase 4 Rip-up And Reroute | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 16522 ; free virtual = 45217 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 16519 ; free virtual = 45215 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 16519 ; free virtual = 45214 Phase 6 Post Hold Fix | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 16520 ; free virtual = 45216 Loading site data... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading site data... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 16495 ; free virtual = 45191 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 16492 ; free virtual = 45188 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 16473 ; free virtual = 45169 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 16507 ; free virtual = 45203 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.039 ; gain = 136.766 ; free physical = 16508 ; free virtual = 45204 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 190af02d6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16502 ; free virtual = 45198 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16492 ; free virtual = 45188 Phase 1.4 Constrain Clocks/Macros Loading route data... Phase 1.4 Constrain Clocks/Macros | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16489 ; free virtual = 45185 Phase 1 Placer Initialization | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16487 ; free virtual = 45183 Phase 2 Global Placement Loading route data... Processing options... Creating bitmap... Writing placer database... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2130.039 ; gain = 0.000 ; free physical = 16442 ; free virtual = 45142 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 16391 ; free virtual = 45089 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 16361 ; free virtual = 45059 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 16361 ; free virtual = 45059 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:01:04 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:44 . Memory (MB): peak = 2606.902 ; gain = 389.621 ; free physical = 16361 ; free virtual = 45060 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:01:04 2019... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 17f6b07bf Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 16397 ; free virtual = 45095 Phase 3 Initial Routing Bitstream size: 4243411 bytes Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17482 ; free virtual = 46180 Config size: 1060815 words Number of configuration frames: 9996 Creating bitstream... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17481 ; free virtual = 46180 Phase 4 Rip-up And Reroute | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17481 ; free virtual = 46180 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17481 ; free virtual = 46180 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter DONE Phase 6.1 Hold Fix Iter | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17485 ; free virtual = 46184 Phase 6 Post Hold Fix | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17484 ; free virtual = 46183 Creating bitstream... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17476 ; free virtual = 46175 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17474 ; free virtual = 46173 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17468 ; free virtual = 46167 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 17506 ; free virtual = 46205 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2140.020 ; gain = 55.477 ; free physical = 17501 ; free virtual = 46201 touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.50 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 17377 ; free virtual = 46079 Phase 2 Global Placement | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17390 ; free virtual = 46094 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17361 ; free virtual = 46065 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b3a364ee Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17349 ; free virtual = 46050 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d7e42b9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17323 ; free virtual = 46025 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 15732a31e Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17293 ; free virtual = 45994 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17331 ; free virtual = 46032 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17326 ; free virtual = 46027 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17319 ; free virtual = 46020 Phase 3 Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17315 ; free virtual = 46016 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17336 ; free virtual = 46038 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17347 ; free virtual = 46049 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17340 ; free virtual = 46042 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17331 ; free virtual = 46033 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17325 ; free virtual = 46027 Loading site data... Ending Placer Task | Checksum: 181b67064 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 17330 ; free virtual = 46032 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 659.605 ; free physical = 17330 ; free virtual = 46032 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.254 ; gain = 384.367 ; free physical = 17604 ; free virtual = 46315 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado 12-1842] Bitgen Completed Successfully. Starting Routing Task INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9d16c75a ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.957 ; gain = 0.000 ; free physical = 17659 ; free virtual = 46371 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1549.957 ; gain = 0.000 ; free physical = 17581 ; free virtual = 46293 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 17378 ; free virtual = 46090 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:01:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2471.363 ; gain = 345.105 ; free physical = 17390 ; free virtual = 46103 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:01:13 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:01:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2471.363 ; gain = 344.105 ; free physical = 18329 ; free virtual = 47042 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:01:13 2019... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 151febe35 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18336 ; free virtual = 47049 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18340 ; free virtual = 47053 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18353 ; free virtual = 47066 Phase 1 Placer Initialization | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18363 ; free virtual = 47076 Phase 2 Global Placement touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 1e13a2cde Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18971 ; free virtual = 47688 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18970 ; free virtual = 47687 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 262698c70 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18970 ; free virtual = 47686 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23c446a3b Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18968 ; free virtual = 47685 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 205f8caa0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18967 ; free virtual = 47684 Phase 3.5 Small Shape Detail Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Phase 3.5 Small Shape Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18919 ; free virtual = 47637 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18917 ; free virtual = 47635 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18915 ; free virtual = 47634 Phase 3 Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18911 ; free virtual = 47631 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18908 ; free virtual = 47629 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18929 ; free virtual = 47651 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18940 ; free virtual = 47661 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18957 ; free virtual = 47678 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1eba3aebc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18961 ; free virtual = 47682 Ending Placer Task | Checksum: 1a3769583 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 18985 ; free virtual = 47706 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 18984 ; free virtual = 47705 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15487 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 168520de7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.070 ; gain = 50.668 ; free physical = 19145 ; free virtual = 47867 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 168520de7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.059 ; gain = 60.656 ; free physical = 19048 ; free virtual = 47771 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 168520de7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.059 ; gain = 60.656 ; free physical = 19047 ; free virtual = 47769 Number of Nodes with overlaps = 0 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading site data... Phase 2 Router Initialization | Checksum: 15eed57fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18889 ; free virtual = 47612 Phase 3 Initial Routing Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: bed6ec79 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Loading route data... Phase 3 Initial Routing | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18877 ; free virtual = 47600 Processing options... Creating bitmap... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18856 ; free virtual = 47579 Phase 4 Rip-up And Reroute | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18851 ; free virtual = 47573 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18836 ; free virtual = 47559 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18835 ; free virtual = 47558 Phase 6 Post Hold Fix | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18831 ; free virtual = 47554 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18764 ; free virtual = 47487 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18754 ; free virtual = 47477 Phase 9 Depositing Routes INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:01:21 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2460.109 ; gain = 339.105 ; free physical = 18841 ; free virtual = 47565 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:01:21 2019... Phase 9 Depositing Routes | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18850 ; free virtual = 47573 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.488 ; gain = 95.086 ; free physical = 18893 ; free virtual = 47616 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 2217.277 ; gain = 165.891 ; free physical = 18897 ; free virtual = 47621 Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Processing options... Creating bitmap... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15626 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.277 ; gain = 0.000 ; free physical = 19559 ; free virtual = 48313 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.277 ; gain = 0.000 ; free physical = 19598 ; free virtual = 48328 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 19187 ; free virtual = 47920 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] Creating bitstream... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 19126 ; free virtual = 47860 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15721 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 19109 ; free virtual = 47844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 19105 ; free virtual = 47840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 19107 ; free virtual = 47842 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 19048 ; free virtual = 47787 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 18975 ; free virtual = 47715 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 19246 ; free virtual = 47990 Phase 1.3 Build Placer Netlist Model WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19236 ; free virtual = 47981 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19229 ; free virtual = 47974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19227 ; free virtual = 47973 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19230 ; free virtual = 47975 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:01:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2470.145 ; gain = 340.105 ; free physical = 19050 ; free virtual = 47795 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:01:37 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:01:38 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2474.125 ; gain = 334.105 ; free physical = 19985 ; free virtual = 48731 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:01:38 2019... Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15839 touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 20927 ; free virtual = 49674 Phase 1.4 Constrain Clocks/Macros Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15881 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 20909 ; free virtual = 49657 touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 20832 ; free virtual = 49580 Phase 2 Global Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20741 ; free virtual = 49491 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20772 ; free virtual = 49522 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20766 ; free virtual = 49516 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 20749 ; free virtual = 49499 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20655 ; free virtual = 49406 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20655 ; free virtual = 49406 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20653 ; free virtual = 49404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20653 ; free virtual = 49404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20653 ; free virtual = 49404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20653 ; free virtual = 49404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20646 ; free virtual = 49397 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20644 ; free virtual = 49395 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 20645 ; free virtual = 49396 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20590 ; free virtual = 49341 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20594 ; free virtual = 49346 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 20603 ; free virtual = 49355 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 20594 ; free virtual = 49346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 20594 ; free virtual = 49346 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 20593 ; free virtual = 49345 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20578 ; free virtual = 49330 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20535 ; free virtual = 49287 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20508 ; free virtual = 49261 Phase 3.5 Small Shape Detail Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 20448 ; free virtual = 49200 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 20443 ; free virtual = 49195 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20442 ; free virtual = 49194 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20352 ; free virtual = 49105 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20345 ; free virtual = 49099 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20353 ; free virtual = 49106 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20352 ; free virtual = 49105 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20349 ; free virtual = 49102 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20352 ; free virtual = 49105 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20353 ; free virtual = 49106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20354 ; free virtual = 49107 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20354 ; free virtual = 49107 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Phase 3.7 Pipeline Register Optimization Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 20343 ; free virtual = 49096 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 20344 ; free virtual = 49097 INFO: [Project 1-571] Translating synthesized netlist Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20308 ; free virtual = 49061 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20285 ; free virtual = 49039 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20243 ; free virtual = 48996 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 4.2 Post Placement Cleanup 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 20258 ; free virtual = 49011 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20243 ; free virtual = 48996 Phase 4.3 Placer Reporting Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Helper process launched with PID 16732 Phase 4.3 Placer Reporting | Checksum: 181723f81 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20214 ; free virtual = 48968 Phase 4.4 Final Placement Cleanup Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 20200 ; free virtual = 48953 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 20199 ; free virtual = 48953 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20191 ; free virtual = 48945 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20130 ; free virtual = 48883 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 20132 ; free virtual = 48886 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.207 ; gain = 631.953 ; free physical = 20131 ; free virtual = 48885 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 20096 ; free virtual = 48851 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 20048 ; free virtual = 48803 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] Phase 1 Build RT Design WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 19807 ; free virtual = 48567 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 19844 ; free virtual = 48601 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 19842 ; free virtual = 48598 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 19782 ; free virtual = 48538 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 19838 ; free virtual = 48595 --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 19849 ; free virtual = 48606 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 19836 ; free virtual = 48593 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19821 ; free virtual = 48578 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19771 ; free virtual = 48529 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19774 ; free virtual = 48531 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19773 ; free virtual = 48531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19773 ; free virtual = 48531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19772 ; free virtual = 48530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19770 ; free virtual = 48528 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19768 ; free virtual = 48526 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19768 ; free virtual = 48526 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 19769 ; free virtual = 48526 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 19752 ; free virtual = 48510 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 19752 ; free virtual = 48510 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:16] INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 137afd744 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 19630 ; free virtual = 48389 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137afd744 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 19538 ; free virtual = 48297 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137afd744 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 19536 ; free virtual = 48295 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11278bc6b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19569 ; free virtual = 48336 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19575 ; free virtual = 48336 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19591 ; free virtual = 48352 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19579 ; free virtual = 48346 Phase 4 Rip-up And Reroute | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19578 ; free virtual = 48345 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19578 ; free virtual = 48345 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19577 ; free virtual = 48344 Phase 6 Post Hold Fix | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19577 ; free virtual = 48344 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19568 ; free virtual = 48335 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19565 ; free virtual = 48332 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19553 ; free virtual = 48320 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 19590 ; free virtual = 48357 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2141.020 ; gain = 56.477 ; free physical = 19589 ; free virtual = 48356 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19591 ; free virtual = 48352 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 19591 ; free virtual = 48352 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2141.020 ; gain = 0.000 ; free physical = 19577 ; free virtual = 48340 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 19524 ; free virtual = 48286 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 19315 ; free virtual = 48077 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Creating bitstream... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 19216 ; free virtual = 47979 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 19229 ; free virtual = 47993 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 19239 ; free virtual = 48003 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 19239 ; free virtual = 48003 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 19232 ; free virtual = 47996 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 19172 ; free virtual = 47937 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1464.715 ; gain = 0.000 ; free physical = 19172 ; free virtual = 47936 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1464.715 ; gain = 0.000 ; free physical = 19170 ; free virtual = 47935 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 19109 ; free virtual = 47874 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 19128 ; free virtual = 47893 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18955 ; free virtual = 47724 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18959 ; free virtual = 47729 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18964 ; free virtual = 47733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18964 ; free virtual = 47734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18977 ; free virtual = 47746 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18978 ; free virtual = 47747 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18980 ; free virtual = 47749 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18985 ; free virtual = 47754 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18989 ; free virtual = 47758 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16916 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading data files... INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 12358ba72 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 19051 ; free virtual = 47822 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12358ba72 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 19013 ; free virtual = 47784 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12358ba72 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 19013 ; free virtual = 47784 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 18968 ; free virtual = 47739 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 18932 ; free virtual = 47703 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: eb842b41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18906 ; free virtual = 47677 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18872 ; free virtual = 47644 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18862 ; free virtual = 47633 Phase 4 Rip-up And Reroute | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18862 ; free virtual = 47634 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18852 ; free virtual = 47624 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18851 ; free virtual = 47623 Phase 6 Post Hold Fix | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18850 ; free virtual = 47621 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18861 ; free virtual = 47632 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion Congestion Report--------------------------------------------------------------------------------- North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1--------------------------------------------------------------------------------- Area, Max Cong = 8.82353Start Flattening Before IO Insertion %, --------------------------------------------------------------------------------- No Congested Regions. INFO: Helper process launched with PID 16968 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18854 ; free virtual = 47626 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18851 ; free virtual = 47623 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18831 ; free virtual = 47602 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 18865 ; free virtual = 47636 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2141.016 ; gain = 48.473 ; free physical = 18864 ; free virtual = 47635 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 18771 ; free virtual = 47545 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:02:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:03 ; elapsed = 00:00:39 . Memory (MB): peak = 2607.438 ; gain = 390.160 ; free physical = 18760 ; free virtual = 47532 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:02:06 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19750 ; free virtual = 48520 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19747 ; free virtual = 48518 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ DONE --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19777 ; free virtual = 48548 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19775 ; free virtual = 48546 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19772 ; free virtual = 48543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19769 ; free virtual = 48540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19766 ; free virtual = 48537 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19797 ; free virtual = 48568 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 19799 ; free virtual = 48571 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Running DRC as a precondition to command write_bitstream INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 19723 ; free virtual = 48494 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 19633 ; free virtual = 48405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 19528 ; free virtual = 48301 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19523 ; free virtual = 48296 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 19520 ; free virtual = 48293 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 19501 ; free virtual = 48274 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 19498 ; free virtual = 48270 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 19496 ; free virtual = 48269 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 19496 ; free virtual = 48269 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 19496 ; free virtual = 48269 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 19497 ; free virtual = 48270 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 19500 ; free virtual = 48272 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Placer Task WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 19493 ; free virtual = 48271 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 19510 ; free virtual = 48288 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19535 ; free virtual = 48313 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19533 ; free virtual = 48312 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19531 ; free virtual = 48309 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19530 ; free virtual = 48309 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19529 ; free virtual = 48308 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19528 ; free virtual = 48307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19528 ; free virtual = 48306 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 19524 ; free virtual = 48302 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 19524 ; free virtual = 48303 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 19132 ; free virtual = 47912 --------------------------------------------------------------------------------- Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 18784 ; free virtual = 47564 Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6721] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6804] Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 18616 ; free virtual = 47398 Phase 1.3 Build Placer Netlist Model WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 18606 ; free virtual = 47387 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 18605 ; free virtual = 47386 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 18603 ; free virtual = 47384 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 18602 ; free virtual = 47384 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 18603 ; free virtual = 47384 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 18603 ; free virtual = 47384 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 18524 ; free virtual = 47307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 18524 ; free virtual = 47307 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 18525 ; free virtual = 47308 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18525 ; free virtual = 47308 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 18553 ; free virtual = 47336 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18474 ; free virtual = 47258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] Starting Placer Task WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 18334 ; free virtual = 47119 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 18333 ; free virtual = 47118 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 18180 ; free virtual = 46966 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 17860 ; free virtual = 46647 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1549.953 ; gain = 0.000 ; free physical = 17815 ; free virtual = 46602 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:16] Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.39 . Memory (MB): peak = 1549.953 ; gain = 0.000 ; free physical = 17832 ; free virtual = 46620 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 17758 ; free virtual = 46545 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 17759 ; free virtual = 46547 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 17759 ; free virtual = 46547 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 17760 ; free virtual = 46547 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 17760 ; free virtual = 46547 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 17756 ; free virtual = 46543 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 17754 ; free virtual = 46542 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 17744 ; free virtual = 46533 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 18016 ; free virtual = 46809 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 18015 ; free virtual = 46808 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 17791 ; free virtual = 46585 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 17758 ; free virtual = 46553 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17752 ; free virtual = 46547 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:02:26 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2475.125 ; gain = 334.105 ; free physical = 17709 ; free virtual = 46505 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:02:27 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17710 ; free virtual = 46506 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17704 ; free virtual = 46500 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17706 ; free virtual = 46502 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17706 ; free virtual = 46502 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17717 ; free virtual = 46513 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17719 ; free virtual = 46515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17722 ; free virtual = 46518 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 17736 ; free virtual = 46532 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 17742 ; free virtual = 46538 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 17756 ; free virtual = 46551 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 18145 ; free virtual = 46950 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 18120 ; free virtual = 46925 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 18117 ; free virtual = 46922 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 18116 ; free virtual = 46921 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 18112 ; free virtual = 46916 Phase 2 Final Placement Cleanup Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 18101 ; free virtual = 46906 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 18096 ; free virtual = 46901 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 18091 ; free virtual = 46897 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 17969 ; free virtual = 46776 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 18017 ; free virtual = 46826 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18227 ; free virtual = 47036 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Routing Task --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: Launching helper process for spawning children vivado processes Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Helper process launched with PID 17448 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18157 ; free virtual = 46968 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18159 ; free virtual = 46969 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 18187 ; free virtual = 46997 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18185 ; free virtual = 46995 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18183 ; free virtual = 46994 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18180 ; free virtual = 46991 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18179 ; free virtual = 46990 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18178 ; free virtual = 46989 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18178 ; free virtual = 46988 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 18178 ; free virtual = 46988 INFO: [Project 1-571] Translating synthesized netlist Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.965 ; gain = 29.758 ; free physical = 17991 ; free virtual = 46802 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Starting Placer Task Phase 2.1 Fix Topology Constraints INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2134.953 ; gain = 35.746 ; free physical = 17919 ; free virtual = 46730 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2134.953 ; gain = 35.746 ; free physical = 17918 ; free virtual = 46729 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 17912 ; free virtual = 46723 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 17892 ; free virtual = 46703 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.195 ; gain = 0.000 ; free physical = 17833 ; free virtual = 46645 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17836 ; free virtual = 46648 Phase 3 Initial Routing INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 17829 ; free virtual = 46641 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 17827 ; free virtual = 46639 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 17829 ; free virtual = 46641 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17829 ; free virtual = 46640 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17828 ; free virtual = 46639 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17828 ; free virtual = 46639 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17828 ; free virtual = 46639 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17828 ; free virtual = 46639 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17828 ; free virtual = 46639 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 17826 ; free virtual = 46637 Phase 2 Final Placement Cleanup Phase 7 Route finalize Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 17823 ; free virtual = 46635 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 17858 ; free virtual = 46670 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.238 ; gain = 581.562 ; free physical = 17858 ; free virtual = 46669 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17857 ; free virtual = 46669 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17856 ; free virtual = 46667 Phase 9 Depositing Routes INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:02:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17860 ; free virtual = 46672 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.008 ; gain = 54.801 ; free physical = 17897 ; free virtual = 46710 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:51 . Memory (MB): peak = 2192.797 ; gain = 93.590 ; free physical = 17899 ; free virtual = 46711 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.121 ; gain = 334.105 ; free physical = 17901 ; free virtual = 46713 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:02:37 2019... Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.797 ; gain = 0.000 ; free physical = 18376 ; free virtual = 47214 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 18238 ; free virtual = 47054 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2004.156 ; gain = 454.203 ; free physical = 18119 ; free virtual = 46937 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 18120 ; free virtual = 46938 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 18114 ; free virtual = 46933 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.156 ; gain = 454.203 ; free physical = 17818 ; free virtual = 46639 Phase 1.4 Constrain Clocks/Macros Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 17817 ; free virtual = 46638 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.156 ; gain = 454.203 ; free physical = 17779 ; free virtual = 46600 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 17785 ; free virtual = 46606 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.156 ; gain = 454.203 ; free physical = 17805 ; free virtual = 46627 Phase 2 Global Placement INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17552 ; free virtual = 46376 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17583 ; free virtual = 46407 Phase 3.2 Commit Most Macros & LUTRAMs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17512 ; free virtual = 46337 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17565 ; free virtual = 46389 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17550 ; free virtual = 46376 Phase 3.5 Small Shape Detail Placement Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2053.934 ; gain = 120.668 ; free physical = 17496 ; free virtual = 46321 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2059.922 ; gain = 126.656 ; free physical = 17442 ; free virtual = 46267 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2059.922 ; gain = 126.656 ; free physical = 17441 ; free virtual = 46266 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 17433 ; free virtual = 46259 Phase 3 Initial Routing INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18418 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 17412 ; free virtual = 46238 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 17411 ; free virtual = 46237 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 17411 ; free virtual = 46237 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 17411 ; free virtual = 46237 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 17411 ; free virtual = 46237 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 17411 ; free virtual = 46237 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 17350 ; free virtual = 46176 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 17348 ; free virtual = 46174 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 17348 ; free virtual = 46174 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 17408 ; free virtual = 46234 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2107.766 ; gain = 206.516 ; free physical = 17407 ; free virtual = 46233 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2107.766 ; gain = 0.000 ; free physical = 17371 ; free virtual = 46198 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17368 ; free virtual = 46195 Phase 3.6 Re-assign LUT pins INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17284 ; free virtual = 46110 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17137 ; free virtual = 45963 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17110 ; free virtual = 45937 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17140 ; free virtual = 45966 INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream Phase 4.2 Post Placement Cleanup Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 17119 ; free virtual = 45946 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17118 ; free virtual = 45945 Phase 4.3 Placer Reporting Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17110 ; free virtual = 45937 Phase 4.4 Final Placement Cleanup Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 17105 ; free virtual = 45932 Phase 1.3 Build Placer Netlist Model Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17105 ; free virtual = 45932 Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 17104 ; free virtual = 45931 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 17095 ; free virtual = 45922 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 17095 ; free virtual = 45922 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 17094 ; free virtual = 45921 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17096 ; free virtual = 45924 Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 17122 ; free virtual = 45949 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 17127 ; free virtual = 45955 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.203 ; gain = 550.250 ; free physical = 17117 ; free virtual = 45944 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.203 ; gain = 631.953 ; free physical = 17117 ; free virtual = 45944 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] Phase 1 Build RT Design | Checksum: 1016daa37 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 16948 ; free virtual = 45777 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1016daa37 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 16896 ; free virtual = 45724 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1016daa37 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 16895 ; free virtual = 45723 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16937 ; free virtual = 45770 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16819 ; free virtual = 45667 Loading site data... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16806 ; free virtual = 45655 Phase 4 Rip-up And Reroute | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16806 ; free virtual = 45655 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16806 ; free virtual = 45655 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16806 ; free virtual = 45655 Phase 6 Post Hold Fix | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16806 ; free virtual = 45655 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 16825 ; free virtual = 45674 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 16823 ; free virtual = 45672 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 16822 ; free virtual = 45671 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 16855 ; free virtual = 45705 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 16855 ; free virtual = 45705 Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 16858 ; free virtual = 45710 Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 16871 ; free virtual = 45704 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 16654 ; free virtual = 45487 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 16684 ; free virtual = 45516 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18564 Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 16399 ; free virtual = 45233 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 9e4a152e Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2055.930 ; gain = 91.668 ; free physical = 16295 ; free virtual = 45133 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9e4a152e Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.918 ; gain = 96.656 ; free physical = 16293 ; free virtual = 45131 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9e4a152e Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.918 ; gain = 96.656 ; free physical = 16300 ; free virtual = 45139 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15dc3536d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16471 ; free virtual = 45309 Phase 3 Initial Routing Loading data files... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16413 ; free virtual = 45252 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16406 ; free virtual = 45245 Phase 4 Rip-up And Reroute | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16405 ; free virtual = 45244 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16408 ; free virtual = 45247 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16405 ; free virtual = 45244 Phase 6 Post Hold Fix | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16406 ; free virtual = 45245 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 16367 ; free virtual = 45206 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 16365 ; free virtual = 45204 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 16359 ; free virtual = 45198 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 16388 ; free virtual = 45227 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2109.762 ; gain = 177.516 ; free physical = 16386 ; free virtual = 45225 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 16329 ; free virtual = 45169 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1344] INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2136] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1336.070 ; gain = 240.152 ; free physical = 16120 ; free virtual = 44961 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 16009 ; free virtual = 44850 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 15861 ; free virtual = 44704 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:03:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2530.902 ; gain = 338.105 ; free physical = 15850 ; free virtual = 44693 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:03:11 2019... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1345.102 ; gain = 249.184 ; free physical = 15855 ; free virtual = 44698 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1345.102 ; gain = 249.184 ; free physical = 16817 ; free virtual = 45660 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading site data... Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 16809 ; free virtual = 45652 --------------------------------------------------------------------------------- touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16679 ; free virtual = 45528 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:251] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 16668 ; free virtual = 45518 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 16654 ; free virtual = 45504 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 16654 ; free virtual = 45504 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.949 ; gain = 115.504 ; free physical = 16630 ; free virtual = 45480 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16620 ; free virtual = 45471 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 16617 ; free virtual = 45467 Phase 1.4 Constrain Clocks/Macros Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16608 ; free virtual = 45459 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 16571 ; free virtual = 45421 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16567 ; free virtual = 45418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16553 ; free virtual = 45404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16540 ; free virtual = 45391 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16534 ; free virtual = 45384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16520 ; free virtual = 45370 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 16516 ; free virtual = 45367 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.086 ; gain = 257.160 ; free physical = 16517 ; free virtual = 45368 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 16511 ; free virtual = 45362 Phase 2 Global Placement INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.172 ; gain = 44.668 ; free physical = 16667 ; free virtual = 45523 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 16633 ; free virtual = 45489 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 16640 ; free virtual = 45496 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16617 ; free virtual = 45474 Phase 3 Initial Routing WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16587 ; free virtual = 45443 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Creating bitstream... Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16571 ; free virtual = 45427 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16570 ; free virtual = 45427 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16568 ; free virtual = 45425 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16568 ; free virtual = 45425 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16568 ; free virtual = 45425 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16567 ; free virtual = 45424 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 16566 ; free virtual = 45423 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 16564 ; free virtual = 45422 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 16604 ; free virtual = 45461 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2127.254 ; gain = 136.766 ; free physical = 16603 ; free virtual = 45461 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 16577 ; free virtual = 45437 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 16561 ; free virtual = 45419 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 16484 ; free virtual = 45342 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 16483 ; free virtual = 45341 Running DRC as a precondition to command write_bitstream Phase 3.3 Area Swap Optimization Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 16437 ; free virtual = 45296 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:03:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 16472 ; free virtual = 45331 Phase 3.5 Small Shape Detail Placement 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2449.871 ; gain = 342.105 ; free physical = 16485 ; free virtual = 45344 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:03:20 2019... Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2062.922 ; gain = 43.668 ; free physical = 16573 ; free virtual = 45443 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.910 ; gain = 48.656 ; free physical = 16658 ; free virtual = 45531 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.910 ; gain = 48.656 ; free physical = 16698 ; free virtual = 45571 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 39 #of tags: 2 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2077.965 ; gain = 58.711 ; free physical = 17703 ; free virtual = 46587 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 17681 ; free virtual = 46546 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 17662 ; free virtual = 46527 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 17653 ; free virtual = 46518 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 17651 ; free virtual = 46516 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 17646 ; free virtual = 46511 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 17644 ; free virtual = 46510 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 17643 ; free virtual = 46508 Phase 7 Route finalize WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17626 ; free virtual = 46492 Phase 3.6 Re-assign LUT pins Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 17621 ; free virtual = 46489 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 63.711 ; free physical = 17619 ; free virtual = 46488 Phase 9 Depositing Routes Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 63.711 ; free physical = 17653 ; free virtual = 46519 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 63.711 ; free physical = 17689 ; free virtual = 46555 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2121.754 ; gain = 134.516 ; free physical = 17688 ; free virtual = 46554 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17682 ; free virtual = 46558 Phase 3.7 Pipeline Register Optimization Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2121.754 ; gain = 0.000 ; free physical = 17743 ; free virtual = 46632 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17739 ; free virtual = 46628 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 17720 ; free virtual = 46609 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17668 ; free virtual = 46555 Phase 4 Post Placement Optimization and Clean-Up Loading site data... Phase 4.1 Post Commit Optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 17657 ; free virtual = 46544 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17610 ; free virtual = 46497 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17597 ; free virtual = 46485 Phase 4.2 Post Placement Cleanup Loading route data... Processing options... Creating bitmap... Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17548 ; free virtual = 46436 Phase 4.3 Placer Reporting --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 17575 ; free virtual = 46444 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 17581 ; free virtual = 46449 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17553 ; free virtual = 46421 Phase 4.4 Final Placement Cleanup Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17563 ; free virtual = 46432 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17562 ; free virtual = 46431 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17561 ; free virtual = 46429 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17566 ; free virtual = 46435 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17568 ; free virtual = 46437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17568 ; free virtual = 46437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17568 ; free virtual = 46436 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17568 ; free virtual = 46436 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 17577 ; free virtual = 46445 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17584 ; free virtual = 46453 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-571] Translating synthesized netlist Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17542 ; free virtual = 46411 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 17527 ; free virtual = 46396 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 630.953 ; free physical = 17526 ; free virtual = 46395 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:03:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2455.871 ; gain = 345.105 ; free physical = 17501 ; free virtual = 46370 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:03:24 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 18382 ; free virtual = 47259 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 18257 ; free virtual = 47135 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 18155 ; free virtual = 47034 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1585d46d4 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 18154 ; free virtual = 47033 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:03:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 18122 ; free virtual = 47001 --------------------------------------------------------------------------------- 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2452.867 ; gain = 343.105 ; free physical = 18130 ; free virtual = 47009 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:03:32 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 18943 ; free virtual = 47822 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Loading site data... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18791 ; free virtual = 47671 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18700 ; free virtual = 47582 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18698 ; free virtual = 47579 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18658 ; free virtual = 47539 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18653 ; free virtual = 47535 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18675 ; free virtual = 47557 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18673 ; free virtual = 47555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18672 ; free virtual = 47554 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18671 ; free virtual = 47553 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 18673 ; free virtual = 47555 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... Loading site data... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19878 Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 18466 ; free virtual = 47350 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2129.961 ; gain = 29.758 ; free physical = 18736 ; free virtual = 47625 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.949 ; gain = 36.746 ; free physical = 18704 ; free virtual = 47593 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.949 ; gain = 36.746 ; free physical = 18704 ; free virtual = 47593 Phase 1 Build RT Design | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 18692 ; free virtual = 47581 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 18662 ; free virtual = 47551 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 18661 ; free virtual = 47551 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18659 ; free virtual = 47548 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2087.375 ; gain = 61.086 ; free physical = 18674 ; free virtual = 47564 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18676 ; free virtual = 47566 Starting Placer Task Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18677 ; free virtual = 47567 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18677 ; free virtual = 47567 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18677 ; free virtual = 47567 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18677 ; free virtual = 47567 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18677 ; free virtual = 47567 Phase 7 Route finalize INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18670 ; free virtual = 47560 Phase 8 Verifying routed nets Verification completed successfully Phase 1 Placer Initialization Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18668 ; free virtual = 47558 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18662 ; free virtual = 47552 Phase 1.1 Placer Initialization Netlist Sorting INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 18694 ; free virtual = 47583 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2194.793 ; gain = 94.590 ; free physical = 18694 ; free virtual = 47583 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18693 ; free virtual = 47583 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1544.867 ; gain = 0.000 ; free physical = 18692 ; free virtual = 47582 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18694 ; free virtual = 47584 Phase 4 Rip-up And Reroute | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18694 ; free virtual = 47585 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18694 ; free virtual = 47584 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18694 ; free virtual = 47584 Phase 6 Post Hold Fix | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18691 ; free virtual = 47582 Phase 7 Route finalize Writing placer database... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1544.867 ; gain = 0.000 ; free physical = 18691 ; free virtual = 47581 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18689 ; free virtual = 47580 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 18686 ; free virtual = 47578 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 18682 ; free virtual = 47575 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 18720 ; free virtual = 47614 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2130.164 ; gain = 135.891 ; free physical = 18720 ; free virtual = 47613 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Writing placer database... WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing XDEF routing. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:03:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing XDEF routing logical nets. Writing XDEF routing special nets. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2462.430 ; gain = 335.176 ; free physical = 18715 ; free virtual = 47615 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:03:44 2019... Write XDEF Complete: Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 18716 ; free virtual = 47616 Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.793 ; gain = 0.000 ; free physical = 19548 ; free virtual = 48464 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20065 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 19417 ; free virtual = 48316 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20164 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 18975 ; free virtual = 47877 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:03:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2460.859 ; gain = 339.105 ; free physical = 18991 ; free virtual = 47893 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:03:51 2019... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d38ee6f1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19471 ; free virtual = 48374 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19905 ; free virtual = 48808 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19908 ; free virtual = 48811 Phase 1 Placer Initialization | Checksum: 26ae14cd7 Bitstream size: 4243411 bytes Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19908 ; free virtual = 48810 Phase 2 Global Placement Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 262ca559a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19689 ; free virtual = 48595 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 262ca559a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19683 ; free virtual = 48589 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23e660b1f Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19677 ; free virtual = 48583 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 19678 ; free virtual = 48584 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21840e8ea Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19655 ; free virtual = 48562 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e1f5494f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19653 ; free virtual = 48560 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19604 ; free virtual = 48511 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19603 ; free virtual = 48509 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19600 ; free virtual = 48506 Phase 3 Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19601 ; free virtual = 48507 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19600 ; free virtual = 48507 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19600 ; free virtual = 48507 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19600 ; free virtual = 48507 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19591 ; free virtual = 48498 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19590 ; free virtual = 48497 Ending Placer Task | Checksum: 1cc0c8886 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 19603 ; free virtual = 48510 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 19603 ; free virtual = 48510 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] INFO: Launching helper process for spawning children vivado processes WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Helper process launched with PID 21045 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e76cdf7c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 19204 ; free virtual = 48113 --------------------------------------------------------------------------------- 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 19207 ; free virtual = 48116 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 18773 ; free virtual = 47683 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1552.863 ; gain = 0.000 ; free physical = 18760 ; free virtual = 47683 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 18716 ; free virtual = 47639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 18713 ; free virtual = 47637 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.73 . Memory (MB): peak = 1552.863 ; gain = 0.000 ; free physical = 18711 ; free virtual = 47637 INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 18648 ; free virtual = 47560 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 18636 ; free virtual = 47548 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 18494 ; free virtual = 47409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 18492 ; free virtual = 47407 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:16] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 18364 ; free virtual = 47280 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.398 ; gain = 507.531 ; free physical = 18296 ; free virtual = 47212 Phase 1.3 Build Placer Netlist Model WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 18325 ; free virtual = 47242 --------------------------------------------------------------------------------- Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 18402 ; free virtual = 47320 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2130.430 ; gain = 31.227 ; free physical = 18396 ; free virtual = 47315 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 18357 ; free virtual = 47275 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 18357 ; free virtual = 47275 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21240 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 18326 ; free virtual = 47245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 18325 ; free virtual = 47244 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18295 ; free virtual = 47214 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18205 ; free virtual = 47124 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18185 ; free virtual = 47104 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18185 ; free virtual = 47104 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18183 ; free virtual = 47103 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18183 ; free virtual = 47103 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18183 ; free virtual = 47103 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] Phase 7 Route finalize WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18183 ; free virtual = 47103 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18183 ; free virtual = 47102 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18185 ; free virtual = 47105 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 18225 ; free virtual = 47145 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2193.262 ; gain = 94.059 ; free physical = 18225 ; free virtual = 47145 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 18245 ; free virtual = 47166 --------------------------------------------------------------------------------- Writing placer database... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 18238 ; free virtual = 47159 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 18237 ; free virtual = 47159 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 18231 ; free virtual = 47153 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 18707 ; free virtual = 47644 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 507.531 ; free physical = 18658 ; free virtual = 47597 Phase 1.4 Constrain Clocks/Macros Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 507.531 ; free physical = 18671 ; free virtual = 47611 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 507.531 ; free physical = 18661 ; free virtual = 47602 Phase 2 Final Placement Cleanup --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1341.070 ; gain = 245.152 ; free physical = 18665 ; free virtual = 47608 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 507.531 ; free physical = 18658 ; free virtual = 47602 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 18674 ; free virtual = 47618 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 18667 ; free virtual = 47612 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 507.531 ; free physical = 18660 ; free virtual = 47606 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 18653 ; free virtual = 47599 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18611 ; free virtual = 47560 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.262 ; gain = 0.000 ; free physical = 18562 ; free virtual = 47515 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18537 ; free virtual = 47469 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18526 ; free virtual = 47458 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18531 ; free virtual = 47464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18530 ; free virtual = 47462 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18525 ; free virtual = 47457 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18522 ; free virtual = 47454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18518 ; free virtual = 47451 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18510 ; free virtual = 47442 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 18510 ; free virtual = 47443 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 1349.102 ; gain = 253.184 ; free physical = 18550 ; free virtual = 47483 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:04:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.898 ; gain = 338.105 ; free physical = 18555 ; free virtual = 47488 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:04:15 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1349.102 ; gain = 253.184 ; free physical = 18522 ; free virtual = 47454 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement DONE INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:04:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 2470.270 ; gain = 340.105 ; free physical = 19467 ; free virtual = 48400 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:04:16 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20406 ; free virtual = 49340 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 20364 ; free virtual = 49299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 20396 ; free virtual = 49331 --------------------------------------------------------------------------------- touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 20406 ; free virtual = 49341 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: Helper process launched with PID 21523 --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20238 ; free virtual = 49174 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20214 ; free virtual = 49151 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20186 ; free virtual = 49123 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 20181 ; free virtual = 49118 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 20239 ; free virtual = 49175 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20237 ; free virtual = 49174 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20248 ; free virtual = 49184 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20280 ; free virtual = 49217 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20279 ; free virtual = 49215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20273 ; free virtual = 49210 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20272 ; free virtual = 49208 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 20266 ; free virtual = 49203 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1357.086 ; gain = 261.160 ; free physical = 20266 ; free virtual = 49203 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 20217 ; free virtual = 49155 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20207 ; free virtual = 49144 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20198 ; free virtual = 49136 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 20184 ; free virtual = 49122 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 20184 ; free virtual = 49122 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20174 ; free virtual = 49112 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20171 ; free virtual = 49109 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 20170 ; free virtual = 49107 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20170 ; free virtual = 49107 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20167 ; free virtual = 49104 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- No constraint files found. Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20165 ; free virtual = 49102 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20162 ; free virtual = 49099 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20159 ; free virtual = 49096 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20157 ; free virtual = 49095 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 20162 ; free virtual = 49099 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20159 ; free virtual = 49096 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20157 ; free virtual = 49094 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20156 ; free virtual = 49093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20154 ; free virtual = 49092 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20153 ; free virtual = 49090 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20148 ; free virtual = 49085 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 20146 ; free virtual = 49084 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 19431 ; free virtual = 48371 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 19307 ; free virtual = 48248 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 19319 ; free virtual = 48260 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.723 ; gain = 0.000 ; free physical = 19187 ; free virtual = 48130 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1461.723 ; gain = 0.000 ; free physical = 19186 ; free virtual = 48129 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 19188 ; free virtual = 48130 Phase 1.3 Build Placer Netlist Model report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 19208 ; free virtual = 48150 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1551.953 ; gain = 0.000 ; free physical = 19191 ; free virtual = 48134 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1551.953 ; gain = 0.000 ; free physical = 19182 ; free virtual = 48125 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 19123 ; free virtual = 48066 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 19115 ; free virtual = 48058 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19103 ; free virtual = 48046 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18955 ; free virtual = 47899 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18972 ; free virtual = 47916 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18971 ; free virtual = 47915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18954 ; free virtual = 47899 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18863 ; free virtual = 47808 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18854 ; free virtual = 47798 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18841 ; free virtual = 47786 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18838 ; free virtual = 47782 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18832 ; free virtual = 47777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18828 ; free virtual = 47773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18824 ; free virtual = 47769 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18813 ; free virtual = 47758 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 18813 ; free virtual = 47757 INFO: [Project 1-571] Translating synthesized netlist Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading route data... Processing options... Creating bitmap... 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 18784 ; free virtual = 47729 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 18754 ; free virtual = 47699 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 18703 ; free virtual = 47649 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 18688 ; free virtual = 47633 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 18675 ; free virtual = 47621 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 18724 ; free virtual = 47670 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 18722 ; free virtual = 47669 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Placer Task Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 18705 ; free virtual = 47652 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 18686 ; free virtual = 47632 Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 18440 ; free virtual = 47388 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 18685 ; free virtual = 47638 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 18683 ; free virtual = 47636 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 18671 ; free virtual = 47624 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 18657 ; free virtual = 47611 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18654 ; free virtual = 47607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18617 ; free virtual = 47571 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18635 ; free virtual = 47589 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18635 ; free virtual = 47589 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18635 ; free virtual = 47589 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18634 ; free virtual = 47589 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18634 ; free virtual = 47588 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18633 ; free virtual = 47587 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18631 ; free virtual = 47585 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 18633 ; free virtual = 47587 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21825 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21865 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:04:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 2532.367 ; gain = 339.105 ; free physical = 18542 ; free virtual = 47497 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:04:39 2019... INFO: [Project 1-570] Preparing netlist for logic optimization Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1 Build RT Design | Checksum: 15ca2bf97 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 19534 ; free virtual = 48488 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15ca2bf97 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 19505 ; free virtual = 48460 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15ca2bf97 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 19504 ; free virtual = 48460 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: fe41f556 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19361 ; free virtual = 48317 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19395 ; free virtual = 48352 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19393 ; free virtual = 48350 Phase 4 Rip-up And Reroute | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19393 ; free virtual = 48349 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19392 ; free virtual = 48349 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19392 ; free virtual = 48348 Phase 6 Post Hold Fix | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19391 ; free virtual = 48348 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19381 ; free virtual = 48338 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19379 ; free virtual = 48336 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19372 ; free virtual = 48328 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 19406 ; free virtual = 48362 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2140.016 ; gain = 47.473 ; free physical = 19404 ; free virtual = 48361 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 19330 ; free virtual = 48289 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 19340 ; free virtual = 48298 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 19142 ; free virtual = 48101 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 18929 ; free virtual = 47888 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1557.859 ; gain = 0.000 ; free physical = 18900 ; free virtual = 47858 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.64 . Memory (MB): peak = 1557.859 ; gain = 0.000 ; free physical = 18867 ; free virtual = 47826 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 18839 ; free virtual = 47799 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 18835 ; free virtual = 47794 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 470.531 ; free physical = 18701 ; free virtual = 47661 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 470.531 ; free physical = 18687 ; free virtual = 47647 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 470.531 ; free physical = 18685 ; free virtual = 47645 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 470.531 ; free physical = 18683 ; free virtual = 47643 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 470.531 ; free physical = 18682 ; free virtual = 47641 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 470.531 ; free physical = 18675 ; free virtual = 47635 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 18675 ; free virtual = 47635 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 18566 ; free virtual = 47525 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 18457 ; free virtual = 47418 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 18273 ; free virtual = 47234 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18271 ; free virtual = 47233 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 18259 ; free virtual = 47222 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18227 ; free virtual = 47190 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18226 ; free virtual = 47189 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18208 ; free virtual = 47170 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1889] INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 17811 ; free virtual = 46775 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 17811 ; free virtual = 46775 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 17788 ; free virtual = 46753 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 17787 ; free virtual = 46752 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 17701 ; free virtual = 46667 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 17695 ; free virtual = 46660 Phase 1.4 Constrain Clocks/Macros WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 17715 ; free virtual = 46680 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 17665 ; free virtual = 46631 Phase 1.3 Build Placer Netlist Model Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 17616 ; free virtual = 46582 Phase 2 Global Placement INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Build RT Design | Checksum: 1a631b8be Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2136.082 ; gain = 51.668 ; free physical = 17244 ; free virtual = 46211 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1902.453 ; gain = 0.000 ; free physical = 17249 ; free virtual = 46216 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1a631b8be Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2146.070 ; gain = 61.656 ; free physical = 17194 ; free virtual = 46162 Phase 2.2 Pre Route Cleanup WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2.2 Pre Route Cleanup | Checksum: 1a631b8be Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2146.070 ; gain = 61.656 ; free physical = 17193 ; free virtual = 46161 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.496 ; gain = 518.531 ; free physical = 17161 ; free virtual = 46129 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.496 ; gain = 518.531 ; free physical = 17156 ; free virtual = 46124 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.496 ; gain = 518.531 ; free physical = 17144 ; free virtual = 46112 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.496 ; gain = 518.531 ; free physical = 17146 ; free virtual = 46114 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.496 ; gain = 518.531 ; free physical = 17143 ; free virtual = 46111 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.496 ; gain = 518.531 ; free physical = 17144 ; free virtual = 46112 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.496 ; gain = 583.562 ; free physical = 17142 ; free virtual = 46110 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18b270a8f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17092 ; free virtual = 46060 Phase 3 Initial Routing Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 17063 ; free virtual = 46032 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17055 ; free virtual = 46025 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17050 ; free virtual = 46020 Phase 4 Rip-up And Reroute | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17047 ; free virtual = 46017 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17046 ; free virtual = 46015 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17046 ; free virtual = 46015 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 17047 ; free virtual = 46016 Phase 3.2 Commit Most Macros & LUTRAMs Phase 6 Post Hold Fix | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17045 ; free virtual = 46014 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17027 ; free virtual = 45997 Phase 8 Verifying routed nets Verification completed successfully Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 17024 ; free virtual = 45994 Phase 1.4 Constrain Clocks/Macros Phase 8 Verifying routed nets | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17025 ; free virtual = 45994 Phase 9 Depositing Routes Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 17004 ; free virtual = 45973 Phase 3.3 Area Swap Optimization Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 16997 ; free virtual = 45967 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 9 Depositing Routes | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 16992 ; free virtual = 45962 Phase 1 Build RT Design INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2180.500 ; gain = 96.086 ; free physical = 17034 ; free virtual = 46004 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:46 . Memory (MB): peak = 2219.289 ; gain = 166.891 ; free physical = 17032 ; free virtual = 46002 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 17023 ; free virtual = 45994 Phase 2 Global Placement Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 17016 ; free virtual = 45988 Phase 3.4 Pipeline Register Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16959 ; free virtual = 45932 Phase 3.5 Small Shape Detail Placement Loading site data... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 16945 ; free virtual = 45919 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 16914 ; free virtual = 45890 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading route data... Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16908 ; free virtual = 45886 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16825 ; free virtual = 45811 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16826 ; free virtual = 45813 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16828 ; free virtual = 45816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16827 ; free virtual = 45817 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16827 ; free virtual = 45816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16826 ; free virtual = 45817 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16826 ; free virtual = 45817 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16824 ; free virtual = 45816 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16824 ; free virtual = 45816 Phase 3.6 Re-assign LUT pins Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 16823 ; free virtual = 45815 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16791 ; free virtual = 45781 Phase 3.7 Pipeline Register Optimization WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 16788 ; free virtual = 45778 --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16784 ; free virtual = 45774 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16778 ; free virtual = 45771 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 16775 ; free virtual = 45768 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16771 ; free virtual = 45765 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16771 ; free virtual = 45765 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16765 ; free virtual = 45761 Phase 4.3 Placer Reporting Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16677 ; free virtual = 45677 Phase 4.4 Final Placement Cleanup Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 16676 ; free virtual = 45676 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2219.289 ; gain = 0.000 ; free physical = 16676 ; free virtual = 45678 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16675 ; free virtual = 45678 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 16674 ; free virtual = 45677 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Project 1-570] Preparing netlist for logic optimization Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16647 ; free virtual = 45650 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16672 ; free virtual = 45675 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16670 ; free virtual = 45673 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16666 ; free virtual = 45669 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16664 ; free virtual = 45667 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16662 ; free virtual = 45666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16661 ; free virtual = 45665 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16661 ; free virtual = 45665 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 16660 ; free virtual = 45663 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 16660 ; free virtual = 45664 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 16658 ; free virtual = 45662 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 16657 ; free virtual = 45661 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 16621 ; free virtual = 45625 Phase 3.3 Area Swap Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2219.289 ; gain = 0.000 ; free physical = 16555 ; free virtual = 45534 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 16548 ; free virtual = 45526 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 16504 ; free virtual = 45483 Phase 3.5 Small Shape Detail Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: Launching helper process for spawning children vivado processes INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: Helper process launched with PID 23607 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Timing 38-35] Done setting XDC timing constraints. Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.203 ; gain = 0.000 ; free physical = 15815 ; free virtual = 44796 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15814 ; free virtual = 44795 Phase 3.6 Re-assign LUT pins Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 15874 ; free virtual = 44856 Phase 1.3 Build Placer Netlist Model Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15871 ; free virtual = 44853 Phase 3.7 Pipeline Register Optimization Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 15868 ; free virtual = 44850 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 15863 ; free virtual = 44845 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 15860 ; free virtual = 44842 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 15857 ; free virtual = 44839 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 15857 ; free virtual = 44839 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.246 ; gain = 580.562 ; free physical = 15873 ; free virtual = 44855 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15937 ; free virtual = 44919 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15957 ; free virtual = 44940 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 15990 ; free virtual = 44973 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15990 ; free virtual = 44973 INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15982 ; free virtual = 44965 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15974 ; free virtual = 44958 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15973 ; free virtual = 44957 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 15971 ; free virtual = 44955 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15969 ; free virtual = 44952 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.207 ; gain = 558.254 ; free physical = 15989 ; free virtual = 44974 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2107.207 ; gain = 639.957 ; free physical = 15987 ; free virtual = 44972 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 16169 ; free virtual = 45158 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 16169 ; free virtual = 45157 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 16131 ; free virtual = 45121 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 16156 ; free virtual = 45146 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 16102 ; free virtual = 45093 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 16101 ; free virtual = 45092 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:05:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2474.121 ; gain = 334.105 ; free physical = 16061 ; free virtual = 45052 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:05:14 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 16791 ; free virtual = 45785 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 16857 ; free virtual = 45851 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 16855 ; free virtual = 45849 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 16843 ; free virtual = 45837 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 16785 ; free virtual = 45779 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1 Build RT Design | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.078 ; gain = 51.668 ; free physical = 16782 ; free virtual = 45776 Loading data files... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 16770 ; free virtual = 45764 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 16764 ; free virtual = 45759 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2146.066 ; gain = 61.656 ; free physical = 16668 ; free virtual = 45662 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2146.066 ; gain = 61.656 ; free physical = 16666 ; free virtual = 45660 Number of Nodes with overlaps = 0 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] Phase 2 Router Initialization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16507 ; free virtual = 45502 Phase 3 Initial Routing WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16445 ; free virtual = 45440 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16419 ; free virtual = 45415 WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 4 Rip-up And Reroute | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16405 ; free virtual = 45401 Phase 5 Delay and Skew Optimization INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] Phase 5 Delay and Skew Optimization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16404 ; free virtual = 45400 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16406 ; free virtual = 45402 Phase 6 Post Hold Fix | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16410 ; free virtual = 45407 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16426 ; free virtual = 45424 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16430 ; free virtual = 45434 Phase 9 Depositing Routes report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 16453 ; free virtual = 45450 --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 16447 ; free virtual = 45445 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 16447 ; free virtual = 45445 --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 9 Depositing Routes | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16447 ; free virtual = 45445 Phase 1 Build RT Design INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2181.496 ; gain = 97.086 ; free physical = 16489 ; free virtual = 45487 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2220.285 ; gain = 167.891 ; free physical = 16489 ; free virtual = 45487 INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 16429 ; free virtual = 45431 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2220.285 ; gain = 0.000 ; free physical = 16254 ; free virtual = 45283 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2220.285 ; gain = 0.000 ; free physical = 16248 ; free virtual = 45253 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 15868 ; free virtual = 44876 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 15744 ; free virtual = 44752 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15671 ; free virtual = 44679 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 15561 ; free virtual = 44570 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15536 ; free virtual = 44546 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 15536 ; free virtual = 44546 Phase 1.3 Build Placer Netlist Model Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15533 ; free virtual = 44543 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15539 ; free virtual = 44549 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15536 ; free virtual = 44546 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15534 ; free virtual = 44543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15532 ; free virtual = 44542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 15530 ; free virtual = 44540 Phase 1.4 Constrain Clocks/Macros Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15516 ; free virtual = 44526 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15511 ; free virtual = 44522 Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 15505 ; free virtual = 44515 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 15491 ; free virtual = 44501 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 15514 ; free virtual = 44524 Phase 2 Final Placement Cleanup INFO: [Project 1-571] Translating synthesized netlist Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 15501 ; free virtual = 44511 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 15499 ; free virtual = 44510 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 15499 ; free virtual = 44510 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2057.938 ; gain = 93.668 ; free physical = 15374 ; free virtual = 44388 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.926 ; gain = 99.656 ; free physical = 15293 ; free virtual = 44306 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.926 ; gain = 99.656 ; free physical = 15293 ; free virtual = 44306 INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15266 ; free virtual = 44280 Phase 3 Initial Routing WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15217 ; free virtual = 44231 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15201 ; free virtual = 44215 Phase 4 Rip-up And Reroute | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15200 ; free virtual = 44214 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15199 ; free virtual = 44213 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15198 ; free virtual = 44213 Phase 6 Post Hold Fix | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15191 ; free virtual = 44206 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 15139 ; free virtual = 44153 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.980 ; gain = 109.711 ; free physical = 15135 ; free virtual = 44150 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.980 ; gain = 109.711 ; free physical = 15127 ; free virtual = 44141 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.980 ; gain = 109.711 ; free physical = 15155 ; free virtual = 44170 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2112.770 ; gain = 180.516 ; free physical = 15146 ; free virtual = 44160 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2112.770 ; gain = 0.000 ; free physical = 15082 ; free virtual = 44098 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 15019 ; free virtual = 44034 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 15077 ; free virtual = 44093 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 15075 ; free virtual = 44091 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 15077 ; free virtual = 44093 Running DRC as a precondition to command write_bitstream Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 15077 ; free virtual = 44093 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 15077 ; free virtual = 44093 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 15078 ; free virtual = 44093 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 15078 ; free virtual = 44093 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 14844 ; free virtual = 43861 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24110 Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 14720 ; free virtual = 43738 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 14711 ; free virtual = 43729 Loading data files... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.180 ; gain = 44.668 ; free physical = 14752 ; free virtual = 43776 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2075.168 ; gain = 52.656 ; free physical = 14719 ; free virtual = 43743 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2075.168 ; gain = 52.656 ; free physical = 14719 ; free virtual = 43742 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14680 ; free virtual = 43704 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.473 ; gain = 63.961 ; free physical = 14638 ; free virtual = 43662 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.473 ; gain = 63.961 ; free physical = 14635 ; free virtual = 43659 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.473 ; gain = 63.961 ; free physical = 14635 ; free virtual = 43659 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.473 ; gain = 63.961 ; free physical = 14634 ; free virtual = 43658 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.473 ; gain = 63.961 ; free physical = 14633 ; free virtual = 43658 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.473 ; gain = 63.961 ; free physical = 14633 ; free virtual = 43657 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.473 ; gain = 63.961 ; free physical = 14611 ; free virtual = 43635 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2089.473 ; gain = 66.961 ; free physical = 14610 ; free virtual = 43635 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2090.473 ; gain = 67.961 ; free physical = 14590 ; free virtual = 43614 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2090.473 ; gain = 67.961 ; free physical = 14618 ; free virtual = 43642 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2129.262 ; gain = 138.766 ; free physical = 14616 ; free virtual = 43641 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2129.262 ; gain = 0.000 ; free physical = 14539 ; free virtual = 43567 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:05:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2608.449 ; gain = 389.160 ; free physical = 14550 ; free virtual = 43578 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:05:49 2019... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 15412 ; free virtual = 44439 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2129.961 ; gain = 30.758 ; free physical = 15382 ; free virtual = 44409 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 15355 ; free virtual = 44383 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 15356 ; free virtual = 44384 Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15233 ; free virtual = 44261 Phase 3 Initial Routing Loading route data... Processing options... Creating bitmap... Loading site data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15226 ; free virtual = 44254 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15220 ; free virtual = 44249 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15220 ; free virtual = 44249 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15219 ; free virtual = 44248 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15218 ; free virtual = 44247 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15218 ; free virtual = 44247 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Loading route data... Processing options... Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15180 ; free virtual = 44208 Phase 8 Verifying routed nets Creating bitmap... Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15174 ; free virtual = 44202 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15169 ; free virtual = 44198 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 15202 ; free virtual = 44230 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 2193.793 ; gain = 94.590 ; free physical = 15198 ; free virtual = 44226 Writing placer database... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:139] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 15152 ; free virtual = 44186 --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 15168 ; free virtual = 44204 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 15168 ; free virtual = 44204 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 15152 ; free virtual = 44189 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.930 ; gain = 43.668 ; free physical = 15089 ; free virtual = 44130 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Creating bitstream... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.918 ; gain = 48.656 ; free physical = 15049 ; free virtual = 44090 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.918 ; gain = 48.656 ; free physical = 15048 ; free virtual = 44089 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2077.973 ; gain = 59.711 ; free physical = 14994 ; free virtual = 44039 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 14959 ; free virtual = 44007 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 14953 ; free virtual = 44002 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 14952 ; free virtual = 44001 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 14952 ; free virtual = 44001 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 14951 ; free virtual = 44000 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 14950 ; free virtual = 44000 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 14931 ; free virtual = 43982 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 14930 ; free virtual = 43981 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 14928 ; free virtual = 43980 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 14964 ; free virtual = 44015 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2120.762 ; gain = 134.516 ; free physical = 14963 ; free virtual = 44015 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.793 ; gain = 0.000 ; free physical = 14959 ; free virtual = 44013 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2120.762 ; gain = 0.000 ; free physical = 14953 ; free virtual = 44010 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2193.793 ; gain = 0.000 ; free physical = 14965 ; free virtual = 43999 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2128.961 ; gain = 21.754 ; free physical = 15095 ; free virtual = 44134 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2135.949 ; gain = 28.742 ; free physical = 15139 ; free virtual = 44179 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2135.949 ; gain = 28.742 ; free physical = 15147 ; free virtual = 44187 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15158 ; free virtual = 44198 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15177 ; free virtual = 44217 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15178 ; free virtual = 44218 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15178 ; free virtual = 44218 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15177 ; free virtual = 44218 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15177 ; free virtual = 44218 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15178 ; free virtual = 44219 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15164 ; free virtual = 44205 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15161 ; free virtual = 44202 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15162 ; free virtual = 44203 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.004 ; gain = 46.797 ; free physical = 15193 ; free virtual = 44234 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2192.793 ; gain = 85.586 ; free physical = 15188 ; free virtual = 44229 Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:06:05 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2454.875 ; gain = 342.105 ; free physical = 14927 ; free virtual = 43981 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:06:05 2019... Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.227 ; gain = 0.000 ; free physical = 15561 ; free virtual = 44624 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.793 ; gain = 0.000 ; free physical = 15491 ; free virtual = 44557 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 15490 ; free virtual = 44556 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 15403 ; free virtual = 44469 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 15428 ; free virtual = 44494 Phase 1.4 Constrain Clocks/Macros Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 15414 ; free virtual = 44481 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 15410 ; free virtual = 44477 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 15458 ; free virtual = 44525 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 15466 ; free virtual = 44533 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15473 ; free virtual = 44540 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 15462 ; free virtual = 44529 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1993.270 ; gain = 576.562 ; free physical = 15458 ; free virtual = 44525 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15322 ; free virtual = 44371 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15318 ; free virtual = 44367 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15313 ; free virtual = 44362 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15312 ; free virtual = 44362 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading route data... Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15313 ; free virtual = 44362 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15314 ; free virtual = 44363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15316 ; free virtual = 44366 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Processing options... Creating bitmap... Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 15391 ; free virtual = 44440 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 15422 ; free virtual = 44471 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1ca097e33 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 15723 ; free virtual = 44772 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 15574 ; free virtual = 44624 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 15571 ; free virtual = 44621 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 130bdaadd Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15571 ; free virtual = 44622 Phase 3 Initial Routing INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15569 ; free virtual = 44620 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15569 ; free virtual = 44620 Phase 4 Rip-up And Reroute | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15568 ; free virtual = 44620 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15568 ; free virtual = 44619 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15568 ; free virtual = 44619 Phase 6 Post Hold Fix | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15559 ; free virtual = 44610 Creating bitstream... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15546 ; free virtual = 44597 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2175.992 ; gain = 91.586 ; free physical = 15536 ; free virtual = 44587 Phase 9 Depositing Routes WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 9 Depositing Routes | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 15506 ; free virtual = 44558 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 15548 ; free virtual = 44600 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:54 . Memory (MB): peak = 2217.781 ; gain = 165.391 ; free physical = 15547 ; free virtual = 44599 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:06:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2608.945 ; gain = 388.660 ; free physical = 15553 ; free virtual = 44604 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:06:12 2019... Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 16738 ; free virtual = 45816 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 16686 ; free virtual = 45773 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading site data... Starting Placer Task INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 16566 ; free virtual = 45628 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15fdaa0f7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 16562 ; free virtual = 45624 Loading route data... Processing options... Creating bitmap... Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:06:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2470.367 ; gain = 341.105 ; free physical = 16376 ; free virtual = 45439 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:06:17 2019... INFO: Launching helper process for spawning children vivado processes Running DRC as a precondition to command write_bitstream INFO: Helper process launched with PID 24644 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 Creating bitstream... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.930 ; gain = 43.668 ; free physical = 17033 ; free virtual = 46101 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 17000 ; free virtual = 46068 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 17000 ; free virtual = 46068 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2078.973 ; gain = 59.711 ; free physical = 17001 ; free virtual = 46070 Phase 3 Initial Routing Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16985 ; free virtual = 46056 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16982 ; free virtual = 46054 Creating bitstream... Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16982 ; free virtual = 46054 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16981 ; free virtual = 46053 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16981 ; free virtual = 46053 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16981 ; free virtual = 46054 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 17046 ; free virtual = 46120 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 17055 ; free virtual = 46128 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 17083 ; free virtual = 46156 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 17129 ; free virtual = 46202 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2121.762 ; gain = 134.516 ; free physical = 17136 ; free virtual = 46209 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2121.762 ; gain = 0.000 ; free physical = 17316 ; free virtual = 46392 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 17202 ; free virtual = 46277 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 17199 ; free virtual = 46274 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 17199 ; free virtual = 46274 Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11706d75b Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.375 ; gain = 61.086 ; free physical = 17113 ; free virtual = 46189 Phase 3 Initial Routing Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17089 ; free virtual = 46165 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17083 ; free virtual = 46159 Phase 4 Rip-up And Reroute | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17083 ; free virtual = 46159 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17082 ; free virtual = 46158 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17080 ; free virtual = 46156 Phase 6 Post Hold Fix | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17079 ; free virtual = 46155 Phase 7 Route finalize Writing bitstream ./design.bit... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17072 ; free virtual = 46152 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 17076 ; free virtual = 46156 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 17132 ; free virtual = 46212 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 17171 ; free virtual = 46251 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2130.164 ; gain = 135.891 ; free physical = 17173 ; free virtual = 46252 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 17393 ; free virtual = 46478 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:06:29 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2532.398 ; gain = 338.605 ; free physical = 17319 ; free virtual = 46403 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:06:29 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 17277 ; free virtual = 46361 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24878 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:83] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 18153 ; free virtual = 47237 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:06:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading data files... 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2461.867 ; gain = 341.105 ; free physical = 18192 ; free virtual = 47276 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:06:31 2019... Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 18200 ; free virtual = 47284 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 18200 ; free virtual = 47284 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 18285 ; free virtual = 47370 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:06:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2532.898 ; gain = 340.105 ; free physical = 18550 ; free virtual = 47644 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:06:36 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 19367 ; free virtual = 48461 touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1dac8b64b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19249 ; free virtual = 48343 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2721b1c31 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19242 ; free virtual = 48336 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2721b1c31 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19233 ; free virtual = 48327 Phase 1 Placer Initialization | Checksum: 2721b1c31 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 19234 ; free virtual = 48330 Phase 2 Global Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 19195 ; free virtual = 48295 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25254 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 19203 ; free virtual = 48304 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 19149 ; free virtual = 48249 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19125 ; free virtual = 48225 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19011 ; free virtual = 48112 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19012 ; free virtual = 48113 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19013 ; free virtual = 48114 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19014 ; free virtual = 48115 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19014 ; free virtual = 48115 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19015 ; free virtual = 48116 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Loading route data... Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19016 ; free virtual = 48117 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19026 ; free virtual = 48127 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 19028 ; free virtual = 48129 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19022 ; free virtual = 48123 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19002 ; free virtual = 48104 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Loading route data... --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19001 ; free virtual = 48103 Processing options... --------------------------------------------------------------------------------- Creating bitmap... INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 18972 ; free virtual = 48074 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 2 Global Placement | Checksum: 26a0424f4 Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18841 ; free virtual = 47944 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26a0424f4 Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18832 ; free virtual = 47935 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22a14ef89 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18829 ; free virtual = 47932 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 203efcd54 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18777 ; free virtual = 47881 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1cda42db9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18773 ; free virtual = 47876 Phase 3.5 Small Shape Detail Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.5 Small Shape Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18766 ; free virtual = 47869 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18753 ; free virtual = 47857 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18749 ; free virtual = 47854 Phase 3 Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18744 ; free virtual = 47848 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18760 ; free virtual = 47864 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18751 ; free virtual = 47856 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18751 ; free virtual = 47855 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18750 ; free virtual = 47854 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 210f6607b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18749 ; free virtual = 47853 INFO: Launching helper process for spawning children vivado processes Ending Placer Task | Checksum: 1c8c94742 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 18767 ; free virtual = 47871 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.539 ; gain = 659.605 ; free physical = 18767 ; free virtual = 47871 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 25844 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Processing options... Starting Routing Task Creating bitmap... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4299e38 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 18363 ; free virtual = 47471 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Placer Task Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 18286 ; free virtual = 47396 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 18285 ; free virtual = 47395 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16bd26d57 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 18281 ; free virtual = 47391 Writing bitstream ./design.bit... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 18552 ; free virtual = 47667 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 18652 ; free virtual = 47767 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18647 ; free virtual = 47762 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6389] Command: synth_design -top top WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6472] Starting synth_design WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6555] Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25960 WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18626 ; free virtual = 47742 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18624 ; free virtual = 47742 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18622 ; free virtual = 47741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18619 ; free virtual = 47739 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18617 ; free virtual = 47738 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18615 ; free virtual = 47737 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18613 ; free virtual = 47737 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18611 ; free virtual = 47735 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 18610 ; free virtual = 47735 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 18535 ; free virtual = 47652 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 18548 ; free virtual = 47664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 18546 ; free virtual = 47663 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 18527 ; free virtual = 47644 ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } --------------------------------------------------------------------------------- ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:06:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 18711 ; free virtual = 47832 --------------------------------------------------------------------------------- 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2460.867 ; gain = 339.105 ; free physical = 18758 ; free virtual = 47879 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:06:56 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26040 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] Phase 1 Build RT Design | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.953 ; gain = 41.668 ; free physical = 19615 ; free virtual = 48738 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing bitstream ./design.bit... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 19607 ; free virtual = 48732 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 19606 ; free virtual = 48731 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19600 ; free virtual = 48724 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19549 ; free virtual = 48677 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19551 ; free virtual = 48679 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19618 ; free virtual = 48746 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 157ee683c Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.246 ; gain = 61.961 ; free physical = 19820 ; free virtual = 48949 Phase 3 Initial Routing INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.246 ; gain = 62.961 ; free physical = 19791 ; free virtual = 48919 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.246 ; gain = 62.961 ; free physical = 19789 ; free virtual = 48917 Phase 4 Rip-up And Reroute | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.246 ; gain = 62.961 ; free physical = 19784 ; free virtual = 48913 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.246 ; gain = 62.961 ; free physical = 19782 ; free virtual = 48911 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.246 ; gain = 62.961 ; free physical = 19782 ; free virtual = 48910 Phase 6 Post Hold Fix | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.246 ; gain = 62.961 ; free physical = 19780 ; free virtual = 48908 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.246 ; gain = 62.961 ; free physical = 19747 ; free virtual = 48876 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2091.246 ; gain = 65.961 ; free physical = 19741 ; free virtual = 48870 Phase 9 Depositing Routes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 9 Depositing Routes | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2091.246 ; gain = 65.961 ; free physical = 19759 ; free virtual = 48887 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 19792 ; free virtual = 48921 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2091.246 ; gain = 65.961 ; free physical = 19799 ; free virtual = 48927 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2130.035 ; gain = 136.766 ; free physical = 19798 ; free virtual = 48927 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2130.035 ; gain = 0.000 ; free physical = 19768 ; free virtual = 48900 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:07:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:44 . Memory (MB): peak = 2605.941 ; gain = 388.160 ; free physical = 19774 ; free virtual = 48904 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:07:00 2019... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task touch build/specimen_006/OK INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 20808 ; free virtual = 49938 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 20808 ; free virtual = 49938 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:07:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.270 ; gain = 340.105 ; free physical = 20701 ; free virtual = 49832 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:07:02 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 21723 ; free virtual = 50860 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 21697 ; free virtual = 50834 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 21689 ; free virtual = 50827 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21691 ; free virtual = 50829 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21491 ; free virtual = 50630 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21486 ; free virtual = 50625 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21482 ; free virtual = 50622 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21480 ; free virtual = 50620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21479 ; free virtual = 50618 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21476 ; free virtual = 50616 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21476 ; free virtual = 50615 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21471 ; free virtual = 50610 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 21483 ; free virtual = 50623 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:55] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 21388 ; free virtual = 50530 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 21351 ; free virtual = 50493 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 21355 ; free virtual = 50497 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26303 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 21369 ; free virtual = 50511 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 21357 ; free virtual = 50498 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 21326 ; free virtual = 50467 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21317 ; free virtual = 50459 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 21297 ; free virtual = 50439 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21173 ; free virtual = 50314 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21165 ; free virtual = 50306 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21158 ; free virtual = 50300 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21158 ; free virtual = 50300 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21157 ; free virtual = 50299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21157 ; free virtual = 50299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21156 ; free virtual = 50298 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21154 ; free virtual = 50295 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 21154 ; free virtual = 50295 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 20512 ; free virtual = 49655 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1487277ac Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 20583 ; free virtual = 49726 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 20573 ; free virtual = 49717 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.4 Constrain Clocks/Macros | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 20569 ; free virtual = 49713 Phase 1 Placer Initialization | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 20565 ; free virtual = 49708 Phase 2 Global Placement INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 20576 ; free virtual = 49720 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:16] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 20469 ; free virtual = 49614 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 20471 ; free virtual = 49616 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 20482 ; free virtual = 49627 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 20498 ; free virtual = 49645 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 20450 ; free virtual = 49596 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 20458 ; free virtual = 49603 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Device 21-403] Loading part xc7z020clg400-1 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 20364 ; free virtual = 49510 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 20241 ; free virtual = 49387 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Starting Placer Task --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20235 ; free virtual = 49382 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 20231 ; free virtual = 49378 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 20302 ; free virtual = 49448 Phase 2 Global Placement | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20270 ; free virtual = 49416 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20264 ; free virtual = 49410 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 24340a58a Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20255 ; free virtual = 49401 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d1b8355 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20243 ; free virtual = 49391 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6cfe3ba Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20243 ; free virtual = 49390 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20113 ; free virtual = 49260 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20104 ; free virtual = 49251 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20095 ; free virtual = 49243 Phase 3 Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20084 ; free virtual = 49231 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20076 ; free virtual = 49223 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20075 ; free virtual = 49222 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ Phase 4.2 Post Placement Cleanup --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20076 ; free virtual = 49223 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.559 ; gain = 81.648 ; free physical = 20075 ; free virtual = 49222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 1abeaee1f --------------------------------------------------------------------------------- Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20073 ; free virtual = 49220 Phase 4.3 Placer Reporting Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20072 ; free virtual = 49219 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20071 ; free virtual = 49218 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20069 ; free virtual = 49217 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20068 ; free virtual = 49216 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20068 ; free virtual = 49216 --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20067 ; free virtual = 49215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20067 ; free virtual = 49214 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20094 ; free virtual = 49241 Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 20134 ; free virtual = 49282 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 20136 ; free virtual = 49284 Ending Placer Task | Checksum: 163bdd4e6 Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20136 ; free virtual = 49284 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 20136 ; free virtual = 49283 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-571] Translating synthesized netlist Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 19939 ; free virtual = 49087 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 7f1e2bdc ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27141 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 19452 ; free virtual = 48603 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 19316 ; free virtual = 48468 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 19313 ; free virtual = 48464 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 19311 ; free virtual = 48463 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 19311 ; free virtual = 48462 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 19311 ; free virtual = 48462 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 19311 ; free virtual = 48463 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 19311 ; free virtual = 48463 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 19243 ; free virtual = 48396 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 19243 ; free virtual = 48395 --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 19240 ; free virtual = 48392 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19150 ; free virtual = 48303 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 19148 ; free virtual = 48301 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cf4d1b03 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 19145 ; free virtual = 48298 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19115 ; free virtual = 48268 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19150 ; free virtual = 48303 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27240 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19128 ; free virtual = 48281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19128 ; free virtual = 48281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19126 ; free virtual = 48279 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19124 ; free virtual = 48278 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19124 ; free virtual = 48277 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19123 ; free virtual = 48277 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 19124 ; free virtual = 48278 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27279 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 19208 ; free virtual = 48368 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 19172 ; free virtual = 48332 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 19138 ; free virtual = 48298 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 19138 ; free virtual = 48298 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4ae2ab4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18997 ; free virtual = 48157 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] Number of Nodes with overlaps = 0 WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] Phase 3 Initial Routing | Checksum: 130e541f3 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18882 ; free virtual = 48043 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] Phase 4 Rip-up And Reroute WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] Phase 4.1 Global Iteration 0 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] Phase 4.1 Global Iteration 0 | Checksum: 130e541f3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18859 ; free virtual = 48020 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] Phase 4 Rip-up And Reroute | Checksum: 130e541f3 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18858 ; free virtual = 48019 Phase 5 Delay and Skew Optimization WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] Phase 5 Delay and Skew Optimization | Checksum: 130e541f3 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18853 ; free virtual = 48014 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130e541f3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18849 ; free virtual = 48010 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] Phase 6 Post Hold Fix | Checksum: 130e541f3 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18844 ; free virtual = 48005 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18840 ; free virtual = 48000 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18839 ; free virtual = 48000 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18865 ; free virtual = 48028 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 18898 ; free virtual = 48063 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2141.016 ; gain = 56.477 ; free physical = 18896 ; free virtual = 48061 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18894 ; free virtual = 48055 --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 18912 ; free virtual = 48080 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18919 ; free virtual = 48083 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18921 ; free virtual = 48085 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:07:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18954 ; free virtual = 48116 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:31 . Memory (MB): peak = 2470.141 ; gain = 340.105 ; free physical = 18954 ; free virtual = 48116 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:07:30 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 19532 ; free virtual = 48697 --------------------------------------------------------------------------------- touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1905.227 ; gain = 0.000 ; free physical = 19469 ; free virtual = 48640 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 19393 ; free virtual = 48580 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 19417 ; free virtual = 48604 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 19411 ; free virtual = 48598 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 19402 ; free virtual = 48589 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 19387 ; free virtual = 48575 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 19372 ; free virtual = 48559 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.270 ; gain = 576.562 ; free physical = 19368 ; free virtual = 48556 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 19278 ; free virtual = 48446 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.094 ; gain = 238.184 ; free physical = 19249 ; free virtual = 48418 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 18981 ; free virtual = 48150 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 18954 ; free virtual = 48123 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18906 ; free virtual = 48075 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18885 ; free virtual = 48054 Phase 1.4 Constrain Clocks/Macros INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18870 ; free virtual = 48039 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18850 ; free virtual = 48019 Phase 2 Final Placement Cleanup Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18865 ; free virtual = 48035 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 18912 ; free virtual = 48081 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 1468.258 ; gain = 385.367 ; free physical = 18912 ; free virtual = 48081 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 18912 ; free virtual = 48081 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 18809 ; free virtual = 47979 --------------------------------------------------------------------------------- Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1550.289 ; gain = 0.000 ; free physical = 18733 ; free virtual = 47903 Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.40 . Memory (MB): peak = 1550.289 ; gain = 0.000 ; free physical = 18717 ; free virtual = 47887 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 18593 ; free virtual = 47765 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 18575 ; free virtual = 47748 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18577 ; free virtual = 47750 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.062 ; gain = 242.152 ; free physical = 18586 ; free virtual = 47758 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18546 ; free virtual = 47719 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18544 ; free virtual = 47717 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18536 ; free virtual = 47709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18534 ; free virtual = 47707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18529 ; free virtual = 47702 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18526 ; free virtual = 47699 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18522 ; free virtual = 47695 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18504 ; free virtual = 47677 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 18502 ; free virtual = 47675 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:16] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18180 ; free virtual = 47354 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1345.094 ; gain = 249.184 ; free physical = 18174 ; free virtual = 47348 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 18140 ; free virtual = 47321 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1345.094 ; gain = 249.184 ; free physical = 18092 ; free virtual = 47273 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18096 ; free virtual = 47271 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 18096 ; free virtual = 47271 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f35ea853 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18058 ; free virtual = 47234 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18056 ; free virtual = 47231 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18055 ; free virtual = 47230 Phase 1 Placer Initialization | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18054 ; free virtual = 47229 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17833 ; free virtual = 47010 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 17583 ; free virtual = 46760 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Loading route data... No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Processing options... Creating bitmap... 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 17603 ; free virtual = 46781 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17657 ; free virtual = 46835 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17648 ; free virtual = 46826 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17630 ; free virtual = 46808 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17633 ; free virtual = 46811 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17634 ; free virtual = 46813 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17632 ; free virtual = 46810 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17632 ; free virtual = 46810 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.070 ; gain = 257.160 ; free physical = 17634 ; free virtual = 46812 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 17637 ; free virtual = 46815 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Global Placement | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17602 ; free virtual = 46781 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17604 ; free virtual = 46783 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 251526ef8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17594 ; free virtual = 46773 Phase 3.3 Area Swap Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.3 Area Swap Optimization | Checksum: 22b2d4cc3 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17581 ; free virtual = 46760 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f4e1ad28 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17582 ; free virtual = 46761 Phase 3.5 Small Shape Detail Placement Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 17577 ; free virtual = 46755 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 17576 ; free virtual = 46755 Phase 3.5 Small Shape Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17538 ; free virtual = 46717 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17537 ; free virtual = 46717 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17535 ; free virtual = 46714 Phase 3 Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17532 ; free virtual = 46712 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17521 ; free virtual = 46700 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17508 ; free virtual = 46687 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17512 ; free virtual = 46691 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17505 ; free virtual = 46684 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17498 ; free virtual = 46677 Ending Placer Task | Checksum: 16e2e720d Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 17471 ; free virtual = 46650 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 17476 ; free virtual = 46655 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 898ec903 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 17437 ; free virtual = 46620 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 17427 ; free virtual = 46631 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 17452 ; free virtual = 46636 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 17452 ; free virtual = 46636 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 17449 ; free virtual = 46633 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17422 ; free virtual = 46607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17274 ; free virtual = 46459 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17289 ; free virtual = 46475 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17273 ; free virtual = 46459 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17271 ; free virtual = 46457 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17265 ; free virtual = 46451 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17268 ; free virtual = 46454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17267 ; free virtual = 46453 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 17264 ; free virtual = 46450 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17265 ; free virtual = 46450 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.777 ; gain = 0.000 ; free physical = 17278 ; free virtual = 46469 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28380 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1341.066 ; gain = 245.152 ; free physical = 17095 ; free virtual = 46287 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.492 ; gain = 453.203 ; free physical = 17064 ; free virtual = 46257 Phase 1.3 Build Placer Netlist Model Phase 1 Build RT Design | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 17046 ; free virtual = 46239 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 17014 ; free virtual = 46207 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 17015 ; free virtual = 46208 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:08:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2474.121 ; gain = 333.105 ; free physical = 16996 ; free virtual = 46189 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:08:02 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 100878403 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17129 ; free virtual = 46323 Phase 3 Initial Routing Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17935 ; free virtual = 47130 touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_013 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17936 ; free virtual = 47131 Phase 4 Rip-up And Reroute | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17936 ; free virtual = 47131 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17935 ; free virtual = 47130 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17934 ; free virtual = 47129 Phase 6 Post Hold Fix | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17934 ; free virtual = 47129 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17919 ; free virtual = 47114 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17917 ; free virtual = 47111 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1349.098 ; gain = 253.184 ; free physical = 17907 ; free virtual = 47101 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17897 ; free virtual = 47092 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 17931 ; free virtual = 47126 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 17929 ; free virtual = 47124 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1349.098 ; gain = 253.184 ; free physical = 17886 ; free virtual = 47082 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 17880 ; free virtual = 47077 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.492 ; gain = 453.203 ; free physical = 17887 ; free virtual = 47084 Phase 1.4 Constrain Clocks/Macros Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17853 ; free virtual = 47050 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.492 ; gain = 453.203 ; free physical = 17841 ; free virtual = 47039 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.492 ; gain = 453.203 ; free physical = 17840 ; free virtual = 47038 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 17808 ; free virtual = 47006 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 17754 ; free virtual = 46952 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 17749 ; free virtual = 46947 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 790be677 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17740 ; free virtual = 46939 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17719 ; free virtual = 46918 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17692 ; free virtual = 46891 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 17644 ; free virtual = 46843 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17631 ; free virtual = 46830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 17626 ; free virtual = 46825 Phase 4 Rip-up And Reroute | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 17625 ; free virtual = 46824 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 17625 ; free virtual = 46824 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 17624 ; free virtual = 46823 Phase 6 Post Hold Fix | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 17624 ; free virtual = 46823 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17634 ; free virtual = 46833 --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17636 ; free virtual = 46835 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17633 ; free virtual = 46832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17633 ; free virtual = 46832 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 17631 ; free virtual = 46830 Phase 8 Verifying routed nets Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.074 ; gain = 261.160 ; free physical = 17628 ; free virtual = 46827 Verification completed successfully Phase 8 Verifying routed nets | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 17630 ; free virtual = 46829 Phase 9 Depositing Routes Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.082 ; gain = 261.160 ; free physical = 17630 ; free virtual = 46829 Phase 9 Depositing Routes | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 17627 ; free virtual = 46826 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 17655 ; free virtual = 46855 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 17652 ; free virtual = 46851 INFO: [Project 1-571] Translating synthesized netlist Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 17681 ; free virtual = 46882 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 17498 ; free virtual = 46698 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 17418 ; free virtual = 46620 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17288 ; free virtual = 46490 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.203 ; gain = 0.000 ; free physical = 17256 ; free virtual = 46458 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17247 ; free virtual = 46449 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 17271 ; free virtual = 46473 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 17266 ; free virtual = 46469 Phase 1.4 Constrain Clocks/Macros WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 17275 ; free virtual = 46477 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 17274 ; free virtual = 46476 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 17275 ; free virtual = 46477 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 17277 ; free virtual = 46479 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 580.562 ; free physical = 17277 ; free virtual = 46479 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17283 ; free virtual = 46485 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 3.3 Area Swap Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 17233 ; free virtual = 46436 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17270 ; free virtual = 46474 Phase 3.4 Pipeline Register Optimization Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.58 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 17306 ; free virtual = 46509 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17299 ; free virtual = 46503 Phase 3.5 Small Shape Detail Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17130 ; free virtual = 46334 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17094 ; free virtual = 46299 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17099 ; free virtual = 46304 Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17096 ; free virtual = 46301 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:16] Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17080 ; free virtual = 46286 Phase 4.2 Post Placement Cleanup INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17112 ; free virtual = 46317 Phase 4.3 Placer Reporting 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:10 . Memory (MB): peak = 1476.828 ; gain = 393.945 ; free physical = 17111 ; free virtual = 46317 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17062 ; free virtual = 46268 Phase 4.4 Final Placement Cleanup WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17093 ; free virtual = 46299 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17052 ; free virtual = 46265 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 17082 ; free virtual = 46289 --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.539 ; gain = 549.250 ; free physical = 17056 ; free virtual = 46266 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.539 ; gain = 631.281 ; free physical = 17055 ; free virtual = 46265 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 17001 ; free virtual = 46208 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 17001 ; free virtual = 46209 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1558.859 ; gain = 0.000 ; free physical = 16830 ; free virtual = 46038 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1558.859 ; gain = 0.000 ; free physical = 16855 ; free virtual = 46063 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 16684 ; free virtual = 45894 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.953 ; gain = 42.668 ; free physical = 16455 ; free virtual = 45666 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 16409 ; free virtual = 45620 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 16409 ; free virtual = 45620 Loading site data... Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.371 ; gain = 62.086 ; free physical = 16277 ; free virtual = 45488 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 16271 ; free virtual = 45483 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 16269 ; free virtual = 45481 Phase 4 Rip-up And Reroute | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 16267 ; free virtual = 45478 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 16266 ; free virtual = 45478 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 16266 ; free virtual = 45477 Phase 6 Post Hold Fix | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 16268 ; free virtual = 45480 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 16246 ; free virtual = 45458 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 16246 ; free virtual = 45458 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.371 ; gain = 67.086 ; free physical = 16241 ; free virtual = 45453 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.371 ; gain = 67.086 ; free physical = 16278 ; free virtual = 45490 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2131.160 ; gain = 137.891 ; free physical = 16276 ; free virtual = 45488 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.60 . Memory (MB): peak = 2131.160 ; gain = 0.000 ; free physical = 16206 ; free virtual = 45422 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 16201 ; free virtual = 45418 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 16157 ; free virtual = 45374 Phase 2.2 Pre Route Cleanup INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 16157 ; free virtual = 45371 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16052 ; free virtual = 45266 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Loading route data... Processing options... Creating bitmap... Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16065 ; free virtual = 45280 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16064 ; free virtual = 45279 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16054 ; free virtual = 45269 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16054 ; free virtual = 45269 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16054 ; free virtual = 45269 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16053 ; free virtual = 45268 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16057 ; free virtual = 45272 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 16055 ; free virtual = 45270 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 16046 ; free virtual = 45262 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 16085 ; free virtual = 45301 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 16085 ; free virtual = 45301 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.60 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 16068 ; free virtual = 45287 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 16000 ; free virtual = 45217 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 15972 ; free virtual = 45190 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15959 ; free virtual = 45178 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29451 Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15776 ; free virtual = 44995 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15809 ; free virtual = 45028 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15775 ; free virtual = 44995 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15779 ; free virtual = 44999 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15785 ; free virtual = 45005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15785 ; free virtual = 45005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15785 ; free virtual = 45005 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 15793 ; free virtual = 45013 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 15802 ; free virtual = 45021 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing bitstream ./design.bit... 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 15970 ; free virtual = 45195 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:08:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 15859 ; free virtual = 45089 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:08:33 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Starting Placer Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 16818 ; free virtual = 46049 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1554.855 ; gain = 0.000 ; free physical = 16756 ; free virtual = 45987 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1554.855 ; gain = 0.000 ; free physical = 16720 ; free virtual = 45951 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 16593 ; free virtual = 45825 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:08:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2475.125 ; gain = 335.105 ; free physical = 16552 ; free virtual = 45785 Phase 1 Build RT Design | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 16551 ; free virtual = 45783 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:08:35 2019... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 16528 ; free virtual = 45760 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 16528 ; free virtual = 45761 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 129e3aa92 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17388 ; free virtual = 46621 Phase 3 Initial Routing touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 17355 ; free virtual = 46589 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17340 ; free virtual = 46573 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17328 ; free virtual = 46561 Phase 4 Rip-up And Reroute | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17327 ; free virtual = 46560 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17325 ; free virtual = 46558 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17323 ; free virtual = 46557 Phase 6 Post Hold Fix | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17314 ; free virtual = 46547 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17281 ; free virtual = 46515 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17273 ; free virtual = 46507 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17236 ; free virtual = 46470 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2104.227 ; gain = 11.684 ; free physical = 17269 ; free virtual = 46504 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2143.016 ; gain = 50.473 ; free physical = 17266 ; free virtual = 46500 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2143.016 ; gain = 0.000 ; free physical = 17067 ; free virtual = 46304 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] Command: report_drc (run_mandatory_drcs) for: bitstream_checks WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 16991 ; free virtual = 46227 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 16971 ; free virtual = 46206 Loading site data... Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 16961 ; free virtual = 46197 Phase 2 Global Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 16951 ; free virtual = 46187 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading route data... 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 16965 ; free virtual = 46201 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Processing options... Creating bitmap... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1546.953 ; gain = 0.000 ; free physical = 16885 ; free virtual = 46123 Loading route data... Processing options... Creating bitmap... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.63 . Memory (MB): peak = 1546.953 ; gain = 0.000 ; free physical = 16857 ; free virtual = 46095 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 16837 ; free virtual = 46075 Phase 1.3 Build Placer Netlist Model WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:16] Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16765 ; free virtual = 46004 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:7] Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16764 ; free virtual = 46003 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16769 ; free virtual = 46015 Loading data files... Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 16773 ; free virtual = 46013 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16780 ; free virtual = 46027 Phase 3.4 Pipeline Register Optimization Creating bitstream... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16759 ; free virtual = 46006 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 16759 ; free virtual = 46000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 16759 ; free virtual = 46000 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 16550 ; free virtual = 45792 Phase 1.4 Constrain Clocks/Macros Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16571 ; free virtual = 45813 Phase 3.6 Re-assign LUT pins Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 16570 ; free virtual = 45812 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 16514 ; free virtual = 45756 Phase 2 Final Placement Cleanup Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16553 ; free virtual = 45795 Phase 3.7 Pipeline Register Optimization Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 16552 ; free virtual = 45794 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 16547 ; free virtual = 45790 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16548 ; free virtual = 45790 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 16494 ; free virtual = 45737 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16472 ; free virtual = 45718 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 16608 ; free virtual = 45854 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16681 ; free virtual = 45928 Phase 4.2 Post Placement Cleanup INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16714 ; free virtual = 45961 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16745 ; free virtual = 45992 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16716 ; free virtual = 45964 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16659 ; free virtual = 45907 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2107.203 ; gain = 558.254 ; free physical = 16758 ; free virtual = 46006 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 2107.203 ; gain = 639.957 ; free physical = 16758 ; free virtual = 46006 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:08:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2462.434 ; gain = 335.176 ; free physical = 16885 ; free virtual = 46138 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:08:52 2019... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 17400 ; free virtual = 46654 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 17393 ; free virtual = 46648 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading route data... Processing options... Creating bitmap... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 17351 ; free virtual = 46606 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17302 ; free virtual = 46557 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:08:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2471.266 ; gain = 340.105 ; free physical = 17275 ; free virtual = 46531 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:08:55 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18305 ; free virtual = 47561 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18300 ; free virtual = 47556 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top DONE ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18298 ; free virtual = 47555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18296 ; free virtual = 47552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18293 ; free virtual = 47550 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18291 ; free virtual = 47548 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18289 ; free virtual = 47546 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 18287 ; free virtual = 47544 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 18288 ; free virtual = 47545 INFO: [Project 1-571] Translating synthesized netlist touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2061.930 ; gain = 43.668 ; free physical = 18179 ; free virtual = 47437 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.918 ; gain = 48.656 ; free physical = 18126 ; free virtual = 47384 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.918 ; gain = 48.656 ; free physical = 18122 ; free virtual = 47380 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 18096 ; free virtual = 47354 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2076.973 ; gain = 58.711 ; free physical = 18075 ; free virtual = 47333 Phase 3 Initial Routing INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 18086 ; free virtual = 47345 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 18110 ; free virtual = 47370 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 18115 ; free virtual = 47375 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d INFO: Launching helper process for spawning children vivado processes Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 18116 ; free virtual = 47375 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 18115 ; free virtual = 47374 INFO: Helper process launched with PID 30671 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 18113 ; free virtual = 47373 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 18108 ; free virtual = 47368 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 18107 ; free virtual = 47367 Phase 9 Depositing Routes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 18099 ; free virtual = 47359 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 18133 ; free virtual = 47393 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2120.762 ; gain = 134.516 ; free physical = 18133 ; free virtual = 47393 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2120.762 ; gain = 0.000 ; free physical = 18092 ; free virtual = 47355 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30746 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2129.766 ; gain = 30.227 ; free physical = 17860 ; free virtual = 47123 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2135.754 ; gain = 36.215 ; free physical = 17800 ; free virtual = 47063 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2135.754 ; gain = 36.215 ; free physical = 17799 ; free virtual = 47063 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17720 ; free virtual = 46984 Phase 3 Initial Routing Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 17720 ; free virtual = 46983 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 17561 ; free virtual = 46825 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17521 ; free virtual = 46785 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17509 ; free virtual = 46773 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17509 ; free virtual = 46773 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17508 ; free virtual = 46772 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17508 ; free virtual = 46772 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17508 ; free virtual = 46772 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17483 ; free virtual = 46747 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17480 ; free virtual = 46744 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17478 ; free virtual = 46742 Phase 1 Placer Initialization | Checksum: 208e4f915 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2153.809 ; gain = 54.270 ; free physical = 17507 ; free virtual = 46772 Routing Is Done. Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 17506 ; free virtual = 46770 Phase 2 Final Placement Cleanup 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 2192.598 ; gain = 93.059 ; free physical = 17505 ; free virtual = 46770 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 17498 ; free virtual = 46763 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Writing placer database... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 17514 ; free virtual = 46780 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 17513 ; free virtual = 46779 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 17442 ; free virtual = 46713 Writing bitstream ./design.bit... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 17594 ; free virtual = 46883 Phase 1.3 Build Placer Netlist Model Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.598 ; gain = 0.000 ; free physical = 17541 ; free virtual = 46835 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 17439 ; free virtual = 46712 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 17456 ; free virtual = 46728 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:09:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2475.121 ; gain = 332.105 ; free physical = 17445 ; free virtual = 46718 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:09:09 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 17470 ; free virtual = 46743 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.953 ; gain = 0.000 ; free physical = 18340 ; free virtual = 47614 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1549.953 ; gain = 0.000 ; free physical = 18322 ; free virtual = 47597 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 18402 ; free virtual = 47677 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 18402 ; free virtual = 47678 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 18385 ; free virtual = 47661 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 18384 ; free virtual = 47660 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 18434 ; free virtual = 47709 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 18433 ; free virtual = 47709 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 18395 ; free virtual = 47670 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 18379 ; free virtual = 47654 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 18364 ; free virtual = 47640 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 18359 ; free virtual = 47635 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 18310 ; free virtual = 47586 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17926 ; free virtual = 47204 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17888 ; free virtual = 47166 Phase 3.2 Commit Most Macros & LUTRAMs Loading site data... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17776 ; free virtual = 47055 Phase 3.3 Area Swap Optimization Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17719 ; free virtual = 46998 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17652 ; free virtual = 46931 Phase 3.5 Small Shape Detail Placement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31609 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17485 ; free virtual = 46766 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17472 ; free virtual = 46753 Phase 3.7 Pipeline Register Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17458 ; free virtual = 46739 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 17452 ; free virtual = 46738 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17456 ; free virtual = 46737 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 17455 ; free virtual = 46736 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17454 ; free virtual = 46735 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17450 ; free virtual = 46732 Phase 4.2 Post Placement Cleanup No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17395 ; free virtual = 46679 Phase 4.3 Placer Reporting --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 17396 ; free virtual = 46678 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 4.3 Placer Reporting | Checksum: 181723f81 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17392 ; free virtual = 46674 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 17392 ; free virtual = 46673 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17389 ; free virtual = 46671 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17383 ; free virtual = 46665 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17369 ; free virtual = 46651 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 17395 ; free virtual = 46677 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 17395 ; free virtual = 46677 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17390 ; free virtual = 46673 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17388 ; free virtual = 46670 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17386 ; free virtual = 46668 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17385 ; free virtual = 46667 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17384 ; free virtual = 46666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17384 ; free virtual = 46666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17388 ; free virtual = 46670 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 17388 ; free virtual = 46670 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 17390 ; free virtual = 46672 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17361 ; free virtual = 46644 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17360 ; free virtual = 46642 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17360 ; free virtual = 46642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17360 ; free virtual = 46642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17359 ; free virtual = 46642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17359 ; free virtual = 46641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17358 ; free virtual = 46640 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 17346 ; free virtual = 46629 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 17335 ; free virtual = 46618 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31778 INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.680 ; gain = 314.797 ; free physical = 17196 ; free virtual = 46485 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 17232 ; free virtual = 46522 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 17196 ; free virtual = 46485 --------------------------------------------------------------------------------- Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 17221 ; free virtual = 46511 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 17221 ; free virtual = 46511 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 17217 ; free virtual = 46508 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 17217 ; free virtual = 46507 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 17162 ; free virtual = 46454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 17147 ; free virtual = 46439 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 17146 ; free virtual = 46438 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 17146 ; free virtual = 46438 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:09:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2459.867 ; gain = 339.105 ; free physical = 17111 ; free virtual = 46403 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:09:30 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 17937 ; free virtual = 47235 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 17952 ; free virtual = 47249 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 17867 ; free virtual = 47166 Phase 1.3 Build Placer Netlist Model INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31995 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:312] Phase 1 Build RT Design | Checksum: 14c2f3401 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:330] Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.074 ; gain = 51.668 ; free physical = 17841 ; free virtual = 47140 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:09:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2531.703 ; gain = 339.105 ; free physical = 17829 ; free virtual = 47129 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:09:35 2019... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 17862 ; free virtual = 47161 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 17868 ; free virtual = 47167 WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2130.957 ; gain = 23.754 ; free physical = 18844 ; free virtual = 48152 touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.945 ; gain = 29.742 ; free physical = 18828 ; free virtual = 48128 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.945 ; gain = 29.742 ; free physical = 18827 ; free virtual = 48127 Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 18827 ; free virtual = 48127 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 18770 ; free virtual = 48070 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18769 ; free virtual = 48069 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18723 ; free virtual = 48023 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18722 ; free virtual = 48023 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18648 ; free virtual = 47948 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18648 ; free virtual = 47948 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18661 ; free virtual = 47962 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18661 ; free virtual = 47962 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18661 ; free virtual = 47961 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18664 ; free virtual = 47964 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18664 ; free virtual = 47964 Number of Nodes with overlaps = 0 Phase 7 Route finalize Phase 3 Initial Routing | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18698 ; free virtual = 47999 Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18692 ; free virtual = 47993 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 4 Rip-up And Reroute | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18690 ; free virtual = 47991 Phase 5 Delay and Skew Optimization Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18690 ; free virtual = 47991 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18688 ; free virtual = 47989 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18684 ; free virtual = 47985 Phase 5 Delay and Skew Optimization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18684 ; free virtual = 47985 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.000 ; gain = 48.797 ; free physical = 18718 ; free virtual = 48018 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2194.789 ; gain = 87.586 ; free physical = 18717 ; free virtual = 48018 Phase 6.1 Hold Fix Iter | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18715 ; free virtual = 48016 Phase 6 Post Hold Fix | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18715 ; free virtual = 48016 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Writing placer database... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18698 ; free virtual = 48000 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18679 ; free virtual = 47982 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18654 ; free virtual = 47958 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2181.492 ; gain = 97.086 ; free physical = 18697 ; free virtual = 48001 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2220.281 ; gain = 167.891 ; free physical = 18695 ; free virtual = 47999 Writing placer database... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 18665 ; free virtual = 47976 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 18639 ; free virtual = 47955 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 18574 ; free virtual = 47896 Phase 2 Global Placement No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 18567 ; free virtual = 47892 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 18559 ; free virtual = 47885 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18553 ; free virtual = 47881 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18517 ; free virtual = 47860 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18508 ; free virtual = 47851 Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.789 ; gain = 0.000 ; free physical = 18508 ; free virtual = 47851 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18505 ; free virtual = 47848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18502 ; free virtual = 47846 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18501 ; free virtual = 47844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18499 ; free virtual = 47842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18500 ; free virtual = 47843 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 18498 ; free virtual = 47841 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 18499 ; free virtual = 47842 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2220.281 ; gain = 0.000 ; free physical = 18411 ; free virtual = 47743 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18401 ; free virtual = 47707 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18342 ; free virtual = 47649 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18409 ; free virtual = 47716 Phase 3.3 Area Swap Optimization Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18400 ; free virtual = 47707 Phase 3.4 Pipeline Register Optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 18433 ; free virtual = 47741 --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18426 ; free virtual = 47734 Phase 3.5 Small Shape Detail Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 18275 ; free virtual = 47583 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 18256 ; free virtual = 47564 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18220 ; free virtual = 47528 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18147 ; free virtual = 47456 Phase 3.6 Re-assign LUT pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 18136 ; free virtual = 47445 --------------------------------------------------------------------------------- 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 18142 ; free virtual = 47451 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18132 ; free virtual = 47441 Phase 3.7 Pipeline Register Optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 18099 ; free virtual = 47409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 18128 ; free virtual = 47437 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18126 ; free virtual = 47436 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18118 ; free virtual = 47428 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18115 ; free virtual = 47425 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18111 ; free virtual = 47420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18110 ; free virtual = 47419 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18102 ; free virtual = 47411 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18101 ; free virtual = 47410 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18100 ; free virtual = 47410 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18098 ; free virtual = 47407 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 18098 ; free virtual = 47407 Phase 3 Detail Placement | Checksum: 181723f81 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 18074 ; free virtual = 47383 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.949 ; gain = 115.508 ; free physical = 18074 ; free virtual = 47383 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 17980 ; free virtual = 47290 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 17838 ; free virtual = 47148 Phase 4.3 Placer Reporting INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 17718 ; free virtual = 47028 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 17599 ; free virtual = 46909 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1845.207 ; gain = 0.000 ; free physical = 17494 ; free virtual = 46805 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 17508 ; free virtual = 46818 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 17510 ; free virtual = 46820 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 17523 ; free virtual = 46834 Loading data files... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 17533 ; free virtual = 46844 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 17533 ; free virtual = 46844 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.199 ; gain = 0.000 ; free physical = 17530 ; free virtual = 46841 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1933.250 ; gain = 471.531 ; free physical = 17390 ; free virtual = 46701 Phase 1.3 Build Placer Netlist Model INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1933.250 ; gain = 471.531 ; free physical = 17382 ; free virtual = 46693 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1933.250 ; gain = 471.531 ; free physical = 17382 ; free virtual = 46693 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1933.250 ; gain = 471.531 ; free physical = 17381 ; free virtual = 46692 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1933.250 ; gain = 471.531 ; free physical = 17375 ; free virtual = 46686 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1933.250 ; gain = 471.531 ; free physical = 17376 ; free virtual = 46687 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1933.250 ; gain = 535.562 ; free physical = 17376 ; free virtual = 46687 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.242 ; gain = 467.531 ; free physical = 17390 ; free virtual = 46701 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.242 ; gain = 467.531 ; free physical = 17384 ; free virtual = 46695 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.242 ; gain = 467.531 ; free physical = 17382 ; free virtual = 46693 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.242 ; gain = 467.531 ; free physical = 17381 ; free virtual = 46693 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.242 ; gain = 467.531 ; free physical = 17382 ; free virtual = 46693 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.242 ; gain = 467.531 ; free physical = 17381 ; free virtual = 46693 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.242 ; gain = 533.562 ; free physical = 17381 ; free virtual = 46693 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: 130471fa6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.070 ; gain = 50.668 ; free physical = 17238 ; free virtual = 46550 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2.1 Fix Topology Constraints Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 2.1 Fix Topology Constraints | Checksum: 130471fa6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 17242 ; free virtual = 46555 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 130471fa6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 17246 ; free virtual = 46558 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 17068 ; free virtual = 46381 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 17007 ; free virtual = 46320 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16992 ; free virtual = 46305 Phase 4 Rip-up And Reroute | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16986 ; free virtual = 46299 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16986 ; free virtual = 46299 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16978 ; free virtual = 46291 Phase 6 Post Hold Fix | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16968 ; free virtual = 46281 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16937 ; free virtual = 46251 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16931 ; free virtual = 46245 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16919 ; free virtual = 46232 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 16959 ; free virtual = 46272 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:48 . Memory (MB): peak = 2218.777 ; gain = 166.391 ; free physical = 16957 ; free virtual = 46270 Writing placer database... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 16836 ; free virtual = 46160 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 16706 ; free virtual = 46039 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: Launching helper process for spawning children vivado processes Starting Placer Task INFO: Helper process launched with PID 538 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 16717 ; free virtual = 46052 --------------------------------------------------------------------------------- Phase 1 Placer Initialization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 16717 ; free virtual = 46052 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 16714 ; free virtual = 46049 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16705 ; free virtual = 46041 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.777 ; gain = 0.000 ; free physical = 16619 ; free virtual = 45962 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16613 ; free virtual = 45957 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16611 ; free virtual = 45955 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16608 ; free virtual = 45953 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16608 ; free virtual = 45953 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16606 ; free virtual = 45951 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16605 ; free virtual = 45950 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16604 ; free virtual = 45949 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 16600 ; free virtual = 45945 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 16600 ; free virtual = 45945 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 657 Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.930 ; gain = 342.047 ; free physical = 15919 ; free virtual = 45243 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 15920 ; free virtual = 45250 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: eeeca7b0 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 15933 ; free virtual = 45262 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 15977 ; free virtual = 45307 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2129.430 ; gain = 30.227 ; free physical = 15897 ; free virtual = 45228 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 15855 ; free virtual = 45185 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 15855 ; free virtual = 45185 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15574 ; free virtual = 44905 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15591 ; free virtual = 44923 WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15583 ; free virtual = 44914 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15582 ; free virtual = 44914 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15582 ; free virtual = 44914 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15582 ; free virtual = 44913 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] Phase 6 Post Hold Fix | Checksum: 8a792087 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15581 ; free virtual = 44913 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 7 Route finalize INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:10:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2533.895 ; gain = 339.105 ; free physical = 15569 ; free virtual = 44901 Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15562 ; free virtual = 44894 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15559 ; free virtual = 44891 Phase 9 Depositing Routes INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:10:09 2019... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15559 ; free virtual = 44891 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.473 ; gain = 54.270 ; free physical = 15593 ; free virtual = 44925 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2192.262 ; gain = 93.059 ; free physical = 15593 ; free virtual = 44925 Writing placer database... INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 16419 ; free virtual = 45755 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 16652 ; free virtual = 45991 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 16635 ; free virtual = 45972 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 16633 ; free virtual = 45970 --------------------------------------------------------------------------------- touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 16628 ; free virtual = 45966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 16566 ; free virtual = 45906 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 16547 ; free virtual = 45887 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 16522 ; free virtual = 45863 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 16527 ; free virtual = 45869 Phase 2 Final Placement Cleanup INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 16536 ; free virtual = 45878 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 16537 ; free virtual = 45879 --------------------------------------------------------------------------------- Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 16527 ; free virtual = 45869 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 16526 ; free virtual = 45868 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 report_drc (run_mandatory_drcs) completed successfully Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] Starting Routing Task WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2192.262 ; gain = 0.000 ; free physical = 16433 ; free virtual = 45791 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 16438 ; free virtual = 45799 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 16436 ; free virtual = 45796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 16435 ; free virtual = 45796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 16430 ; free virtual = 45790 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2192.262 ; gain = 0.000 ; free physical = 16379 ; free virtual = 45718 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 15706 ; free virtual = 45049 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 15674 ; free virtual = 45018 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15641 ; free virtual = 44984 Phase 1.3 Build Placer Netlist Model Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 15638 ; free virtual = 44982 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15634 ; free virtual = 44978 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15631 ; free virtual = 44975 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15630 ; free virtual = 44974 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15624 ; free virtual = 44968 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15620 ; free virtual = 44964 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15619 ; free virtual = 44963 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 15617 ; free virtual = 44961 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15429 ; free virtual = 44774 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15424 ; free virtual = 44768 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15404 ; free virtual = 44748 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15397 ; free virtual = 44741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15397 ; free virtual = 44741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15420 ; free virtual = 44765 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15419 ; free virtual = 44763 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Writing bitstream ./design.bit... Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 15416 ; free virtual = 44760 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 15411 ; free virtual = 44758 INFO: [Project 1-571] Translating synthesized netlist Loading site data... Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Processing options... Creating bitmap... Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 15572 ; free virtual = 44922 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 15574 ; free virtual = 44925 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15589 ; free virtual = 44940 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15441 ; free virtual = 44793 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15440 ; free virtual = 44792 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15440 ; free virtual = 44792 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15439 ; free virtual = 44791 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15439 ; free virtual = 44791 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15439 ; free virtual = 44791 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15438 ; free virtual = 44790 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 15438 ; free virtual = 44790 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 15436 ; free virtual = 44787 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:10:27 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2608.441 ; gain = 388.160 ; free physical = 15357 ; free virtual = 44709 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:10:27 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.449 ; gain = 0.000 ; free physical = 16159 ; free virtual = 45512 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:36 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 16223 ; free virtual = 45577 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b1503975 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 16192 ; free virtual = 45546 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 16190 ; free virtual = 45544 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 16188 ; free virtual = 45542 Phase 1 Placer Initialization | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 16185 ; free virtual = 45539 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 16158 ; free virtual = 45513 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 16158 ; free virtual = 45513 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 15957 ; free virtual = 45314 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15915 ; free virtual = 45272 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15912 ; free virtual = 45269 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2559e6f74 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15907 ; free virtual = 45264 Loading site data... Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22f794d3f Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15902 ; free virtual = 45259 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f92dada4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15900 ; free virtual = 45258 Phase 3.5 Small Shape Detail Placement ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 3.5 Small Shape Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15866 ; free virtual = 45224 Phase 3.6 Re-assign LUT pins INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 15866 ; free virtual = 45224 Phase 3.6 Re-assign LUT pins | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15866 ; free virtual = 45224 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15856 ; free virtual = 45214 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 15856 ; free virtual = 45213 Phase 3 Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15855 ; free virtual = 45212 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15853 ; free virtual = 45210 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15851 ; free virtual = 45208 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15849 ; free virtual = 45207 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15849 ; free virtual = 45206 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15847 ; free virtual = 45205 Ending Placer Task | Checksum: fb45469f Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 15857 ; free virtual = 45215 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.539 ; gain = 667.609 ; free physical = 15857 ; free virtual = 45215 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1910 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 16a59d95 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.430 ; gain = 30.227 ; free physical = 16092 ; free virtual = 45456 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 16040 ; free virtual = 45403 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 16039 ; free virtual = 45402 Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 16002 ; free virtual = 45366 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15991 ; free virtual = 45355 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15991 ; free virtual = 45355 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15991 ; free virtual = 45355 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15991 ; free virtual = 45355 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15991 ; free virtual = 45355 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15991 ; free virtual = 45355 Phase 1 Build RT Design | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2057.934 ; gain = 92.668 ; free physical = 15988 ; free virtual = 45352 Phase 7 Route finalize Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2061.922 ; gain = 96.656 ; free physical = 15957 ; free virtual = 45321 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2061.922 ; gain = 96.656 ; free physical = 15957 ; free virtual = 45321 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15951 ; free virtual = 45315 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15950 ; free virtual = 45314 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15949 ; free virtual = 45314 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15985 ; free virtual = 45349 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2193.262 ; gain = 94.059 ; free physical = 15985 ; free virtual = 45349 Writing placer database... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 106d813e1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 103.711 ; free physical = 15977 ; free virtual = 45344 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 103.711 ; free physical = 15963 ; free virtual = 45333 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 103.711 ; free physical = 15962 ; free virtual = 45332 Phase 4 Rip-up And Reroute | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 103.711 ; free physical = 15962 ; free virtual = 45332 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 103.711 ; free physical = 15962 ; free virtual = 45332 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 103.711 ; free physical = 15962 ; free virtual = 45332 Phase 6 Post Hold Fix | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 103.711 ; free physical = 15962 ; free virtual = 45332 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.977 ; gain = 104.711 ; free physical = 15956 ; free virtual = 45328 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2071.977 ; gain = 106.711 ; free physical = 15955 ; free virtual = 45326 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2071.977 ; gain = 106.711 ; free physical = 15955 ; free virtual = 45327 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2071.977 ; gain = 106.711 ; free physical = 15988 ; free virtual = 45360 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2110.766 ; gain = 177.516 ; free physical = 15987 ; free virtual = 45359 Phase 1 Build RT Design | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2056.926 ; gain = 93.668 ; free physical = 15981 ; free virtual = 45354 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2062.914 ; gain = 99.656 ; free physical = 15947 ; free virtual = 45321 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2062.914 ; gain = 99.656 ; free physical = 15949 ; free virtual = 45322 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 15941 ; free virtual = 45316 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15910 ; free virtual = 45286 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15857 ; free virtual = 45236 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15863 ; free virtual = 45242 Phase 4 Rip-up And Reroute | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15865 ; free virtual = 45243 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15866 ; free virtual = 45244 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15867 ; free virtual = 45245 Phase 6 Post Hold Fix | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15867 ; free virtual = 45246 Phase 7 Route finalize Writing bitstream ./design.bit... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.969 ; gain = 106.711 ; free physical = 15866 ; free virtual = 45247 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2072.969 ; gain = 109.711 ; free physical = 15864 ; free virtual = 45245 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2072.969 ; gain = 109.711 ; free physical = 15864 ; free virtual = 45245 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2072.969 ; gain = 109.711 ; free physical = 15896 ; free virtual = 45277 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2111.758 ; gain = 180.516 ; free physical = 15895 ; free virtual = 45276 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2111.758 ; gain = 0.000 ; free physical = 15980 ; free virtual = 45366 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:10:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2607.938 ; gain = 389.160 ; free physical = 16222 ; free virtual = 45610 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:10:42 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Writing XDEF routing. Number of configuration frames: 9996 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.262 ; gain = 0.000 ; free physical = 17359 ; free virtual = 46753 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:10:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.367 ; gain = 340.105 ; free physical = 17181 ; free virtual = 46561 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:10:45 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 18013 ; free virtual = 47399 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 17736 ; free virtual = 47125 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 17686 ; free virtual = 47074 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 17682 ; free virtual = 47071 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 17697 ; free virtual = 47085 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 17080 ; free virtual = 46470 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 17040 ; free virtual = 46430 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 17026 ; free virtual = 46416 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 17023 ; free virtual = 46413 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 17021 ; free virtual = 46410 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 17018 ; free virtual = 46408 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 17007 ; free virtual = 46397 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 17015 ; free virtual = 46405 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2242 INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.195 ; gain = 0.000 ; free physical = 16633 ; free virtual = 46024 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 16585 ; free virtual = 45976 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 16582 ; free virtual = 45973 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 16579 ; free virtual = 45971 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 16577 ; free virtual = 45968 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 16575 ; free virtual = 45966 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 16574 ; free virtual = 45966 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 580.562 ; free physical = 16573 ; free virtual = 45965 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.480 ; free physical = 16237 ; free virtual = 45631 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.480 ; free physical = 16231 ; free virtual = 45624 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16223 ; free virtual = 45617 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 16202 ; free virtual = 45596 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 16161 ; free virtual = 45555 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 16161 ; free virtual = 45555 Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 16058 ; free virtual = 45452 Phase 3 Initial Routing Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16042 ; free virtual = 45437 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16042 ; free virtual = 45437 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16042 ; free virtual = 45437 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16042 ; free virtual = 45437 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16042 ; free virtual = 45437 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16042 ; free virtual = 45437 Phase 7 Route finalize --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16096 ; free virtual = 45491 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16096 ; free virtual = 45490 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16094 ; free virtual = 45489 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16094 ; free virtual = 45489 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16094 ; free virtual = 45488 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16094 ; free virtual = 45488 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16094 ; free virtual = 45488 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 16088 ; free virtual = 45483 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.918 ; gain = 218.457 ; free physical = 16089 ; free virtual = 45484 Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16089 ; free virtual = 45484 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 16088 ; free virtual = 45482 Phase 9 Depositing Routes INFO: [Project 1-571] Translating synthesized netlist Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 16059 ; free virtual = 45454 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 16096 ; free virtual = 45491 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 16095 ; free virtual = 45490 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 16046 ; free virtual = 45444 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading site data... Loading route data... Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 15886 ; free virtual = 45287 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 16123 ; free virtual = 45532 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 16136 ; free virtual = 45545 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 16133 ; free virtual = 45541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 16142 ; free virtual = 45551 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1404.934 ; gain = 322.039 ; free physical = 16193 ; free virtual = 45601 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading data files... Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.965 ; gain = 0.000 ; free physical = 16019 ; free virtual = 45432 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1470.965 ; gain = 0.000 ; free physical = 16026 ; free virtual = 45439 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2441 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:11:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 16253 ; free virtual = 45667 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:11:08 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_014 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 15c4992dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 17110 ; free virtual = 46526 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15c4992dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 17048 ; free virtual = 46464 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15c4992dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 17047 ; free virtual = 46462 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2568 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b213fb45 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2086.250 ; gain = 59.961 ; free physical = 17056 ; free virtual = 46471 Phase 3 Initial Routing INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:11:10 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2452.863 ; gain = 341.105 ; free physical = 17013 ; free virtual = 46430 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:11:10 2019... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 17016 ; free virtual = 46432 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 17038 ; free virtual = 46454 Phase 4 Rip-up And Reroute | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 17041 ; free virtual = 46457 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 17039 ; free virtual = 46456 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 17039 ; free virtual = 46456 Phase 6 Post Hold Fix | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 17039 ; free virtual = 46455 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 17119 ; free virtual = 46535 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.250 ; gain = 63.961 ; free physical = 17129 ; free virtual = 46546 Phase 9 Depositing Routes Bitstream size: 4243411 bytes Phase 9 Depositing Routes | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.250 ; gain = 63.961 ; free physical = 17977 ; free virtual = 47394 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.250 ; gain = 63.961 ; free physical = 18004 ; free virtual = 47421 Routing Is Done. Config size: 1060815 words 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2129.039 ; gain = 134.766 ; free physical = 18009 ; free virtual = 47426 Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:11:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing placer database... touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2532.367 ; gain = 339.105 ; free physical = 18014 ; free virtual = 47430 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:11:11 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2129.039 ; gain = 0.000 ; free physical = 18044 ; free virtual = 47463 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_013/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 18986 ; free virtual = 48404 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 18975 ; free virtual = 48394 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18973 ; free virtual = 48392 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18853 ; free virtual = 48273 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18848 ; free virtual = 48268 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18842 ; free virtual = 48261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18840 ; free virtual = 48260 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18836 ; free virtual = 48256 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18835 ; free virtual = 48255 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18832 ; free virtual = 48251 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 18830 ; free virtual = 48250 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 18833 ; free virtual = 48253 INFO: [Project 1-571] Translating synthesized netlist Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 18640 ; free virtual = 48061 --------------------------------------------------------------------------------- Loading data files... Creating bitstream... Phase 1 Build RT Design | Checksum: 19d034a6e Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 18533 ; free virtual = 47955 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19d034a6e Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 18497 ; free virtual = 47920 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19d034a6e Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 18498 ; free virtual = 47921 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174587064 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18367 ; free virtual = 47790 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 18334 ; free virtual = 47757 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18282 ; free virtual = 47705 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18276 ; free virtual = 47699 Phase 4 Rip-up And Reroute | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18275 ; free virtual = 47698 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18275 ; free virtual = 47698 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18275 ; free virtual = 47698 Phase 6 Post Hold Fix | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18275 ; free virtual = 47698 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18255 ; free virtual = 47678 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18249 ; free virtual = 47673 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18229 ; free virtual = 47653 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 18265 ; free virtual = 47689 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2141.012 ; gain = 48.473 ; free physical = 18265 ; free virtual = 47689 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2141.012 ; gain = 0.000 ; free physical = 18270 ; free virtual = 47697 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 18232 ; free virtual = 47657 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 18524 ; free virtual = 47952 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 18519 ; free virtual = 47948 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:11:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2472.363 ; gain = 345.105 ; free physical = 18040 ; free virtual = 47471 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:11:25 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.453 ; gain = 0.000 ; free physical = 18852 ; free virtual = 48283 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 Loading data files... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 18797 ; free virtual = 48228 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 18774 ; free virtual = 48205 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 18748 ; free virtual = 48179 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 18755 ; free virtual = 48186 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 18746 ; free virtual = 48177 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.496 ; gain = 515.531 ; free physical = 18737 ; free virtual = 48169 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.496 ; gain = 581.562 ; free physical = 18737 ; free virtual = 48168 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2940 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2985 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 18276 ; free virtual = 47714 --------------------------------------------------------------------------------- Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2061.926 ; gain = 42.668 ; free physical = 18244 ; free virtual = 47682 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.914 ; gain = 48.656 ; free physical = 18204 ; free virtual = 47642 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.914 ; gain = 48.656 ; free physical = 18204 ; free virtual = 47642 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2077.969 ; gain = 58.711 ; free physical = 18152 ; free virtual = 47609 Phase 3 Initial Routing INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3028 Loading site data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 18099 ; free virtual = 47565 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 18086 ; free virtual = 47553 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 18085 ; free virtual = 47552 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 18083 ; free virtual = 47550 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 18082 ; free virtual = 47549 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 18081 ; free virtual = 47549 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 18093 ; free virtual = 47542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 18092 ; free virtual = 47541 --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 18078 ; free virtual = 47530 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 18076 ; free virtual = 47528 Phase 9 Depositing Routes Loading route data... Processing options... Creating bitmap... Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 18037 ; free virtual = 47492 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 18073 ; free virtual = 47528 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2120.758 ; gain = 133.516 ; free physical = 18074 ; free virtual = 47530 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2120.758 ; gain = 0.000 ; free physical = 18063 ; free virtual = 47524 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 18050 ; free virtual = 47491 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 18024 ; free virtual = 47470 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 18037 ; free virtual = 47483 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.922 ; gain = 42.668 ; free physical = 18208 ; free virtual = 47654 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.910 ; gain = 47.656 ; free physical = 18210 ; free virtual = 47656 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.910 ; gain = 47.656 ; free physical = 18208 ; free virtual = 47654 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2075.965 ; gain = 57.711 ; free physical = 18094 ; free virtual = 47541 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 18028 ; free virtual = 47475 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 18022 ; free virtual = 47470 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 18023 ; free virtual = 47470 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 18027 ; free virtual = 47474 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 18032 ; free virtual = 47479 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 18033 ; free virtual = 47480 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 18001 ; free virtual = 47448 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 18034 ; free virtual = 47482 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 18022 ; free virtual = 47470 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 18051 ; free virtual = 47499 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2118.754 ; gain = 132.516 ; free physical = 18049 ; free virtual = 47497 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2118.754 ; gain = 0.000 ; free physical = 17948 ; free virtual = 47399 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 17946 ; free virtual = 47397 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 17650 ; free virtual = 47099 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 17608 ; free virtual = 47057 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:11:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 2471.145 ; gain = 342.105 ; free physical = 17640 ; free virtual = 47089 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:11:43 2019... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 17649 ; free virtual = 47098 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 17675 ; free virtual = 47123 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 17692 ; free virtual = 47140 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 17706 ; free virtual = 47155 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 17714 ; free virtual = 47163 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 17737 ; free virtual = 47187 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 17739 ; free virtual = 47189 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer DONE WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 18417 ; free virtual = 47869 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 1336.070 ; gain = 240.152 ; free physical = 18390 ; free virtual = 47842 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 18392 ; free virtual = 47844 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 18350 ; free virtual = 47806 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 18575 ; free virtual = 48031 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 18604 ; free virtual = 48061 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:16] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 18575 ; free virtual = 48032 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 18573 ; free virtual = 48030 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 18549 ; free virtual = 48006 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18552 ; free virtual = 48009 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18544 ; free virtual = 48009 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18543 ; free virtual = 48007 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18543 ; free virtual = 48007 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18529 ; free virtual = 47987 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.961 ; gain = 115.508 ; free physical = 18513 ; free virtual = 47972 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1347.102 ; gain = 251.184 ; free physical = 18484 ; free virtual = 47949 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18436 ; free virtual = 47894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 18435 ; free virtual = 47894 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1347.102 ; gain = 251.184 ; free physical = 18428 ; free virtual = 47886 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18341 ; free virtual = 47801 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18331 ; free virtual = 47791 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18283 ; free virtual = 47742 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18276 ; free virtual = 47735 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18267 ; free virtual = 47726 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18261 ; free virtual = 47720 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18249 ; free virtual = 47708 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 18248 ; free virtual = 47707 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 18250 ; free virtual = 47709 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:11:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 2475.117 ; gain = 334.105 ; free physical = 18232 ; free virtual = 47692 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:11:50 2019... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18232 ; free virtual = 47692 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 19116 ; free virtual = 48577 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18989 ; free virtual = 48450 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 19002 ; free virtual = 48463 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3337 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18969 ; free virtual = 48430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18939 ; free virtual = 48400 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18983 ; free virtual = 48444 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18966 ; free virtual = 48428 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18964 ; free virtual = 48426 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 18957 ; free virtual = 48418 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.086 ; gain = 259.160 ; free physical = 18956 ; free virtual = 48417 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Loading site data... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 18595 ; free virtual = 48058 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 18591 ; free virtual = 48054 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18578 ; free virtual = 48041 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 18528 ; free virtual = 47991 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 18480 ; free virtual = 47944 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18473 ; free virtual = 47936 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18472 ; free virtual = 47936 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18471 ; free virtual = 47934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18471 ; free virtual = 47934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18458 ; free virtual = 47921 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18454 ; free virtual = 47917 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18470 ; free virtual = 47934 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18470 ; free virtual = 47934 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 18470 ; free virtual = 47933 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 18471 ; free virtual = 47935 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 18439 ; free virtual = 47903 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 18426 ; free virtual = 47890 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18372 ; free virtual = 47837 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18369 ; free virtual = 47833 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18369 ; free virtual = 47833 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18368 ; free virtual = 47832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18367 ; free virtual = 47831 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18345 ; free virtual = 47809 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18343 ; free virtual = 47807 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18337 ; free virtual = 47801 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. INFO: [Project 1-570] Preparing netlist for logic optimization Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18338 ; free virtual = 47802 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.949 ; gain = 246.488 ; free physical = 18327 ; free virtual = 47791 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18333 ; free virtual = 47799 --------------------------------------------------------------------------------- Report Check Netlist: Creating bitstream... +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18332 ; free virtual = 47797 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18318 ; free virtual = 47783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18318 ; free virtual = 47783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18316 ; free virtual = 47781 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18315 ; free virtual = 47780 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18314 ; free virtual = 47779 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 18313 ; free virtual = 47779 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 18315 ; free virtual = 47780 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 18110 ; free virtual = 47576 --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 18108 ; free virtual = 47574 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 18259 ; free virtual = 47730 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 18258 ; free virtual = 47729 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 18282 ; free virtual = 47754 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 18279 ; free virtual = 47750 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 18279 ; free virtual = 47751 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Creating bitstream... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 18278 ; free virtual = 47749 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.941 ; gain = 342.047 ; free physical = 18288 ; free virtual = 47760 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 18061 ; free virtual = 47534 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14eeb77a5 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 18060 ; free virtual = 47533 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:12:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2461.863 ; gain = 341.105 ; free physical = 18007 ; free virtual = 47480 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:12:06 2019... Writing bitstream ./design.bit... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3601 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2062.180 ; gain = 43.668 ; free physical = 19209 ; free virtual = 48690 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.168 ; gain = 48.656 ; free physical = 19170 ; free virtual = 48650 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.168 ; gain = 48.656 ; free physical = 19169 ; free virtual = 48649 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2077.223 ; gain = 58.711 ; free physical = 19108 ; free virtual = 48589 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.223 ; gain = 60.711 ; free physical = 19085 ; free virtual = 48566 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.223 ; gain = 60.711 ; free physical = 19115 ; free virtual = 48596 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.223 ; gain = 60.711 ; free physical = 19120 ; free virtual = 48601 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.223 ; gain = 60.711 ; free physical = 19124 ; free virtual = 48605 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 19124 ; free virtual = 48605 Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.223 ; gain = 60.711 ; free physical = 19124 ; free virtual = 48605 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.223 ; gain = 60.711 ; free physical = 19123 ; free virtual = 48604 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 7 Route finalize INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.223 ; gain = 60.711 ; free physical = 19114 ; free virtual = 48595 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2081.223 ; gain = 62.711 ; free physical = 19114 ; free virtual = 48595 Phase 9 Depositing Routes Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2081.223 ; gain = 62.711 ; free physical = 19108 ; free virtual = 48589 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2081.223 ; gain = 62.711 ; free physical = 19143 ; free virtual = 48624 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2120.012 ; gain = 133.516 ; free physical = 19144 ; free virtual = 48626 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:12:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing placer database... 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 2459.859 ; gain = 341.105 ; free physical = 19121 ; free virtual = 48603 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:12:11 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2120.012 ; gain = 0.000 ; free physical = 19138 ; free virtual = 48622 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 20034 ; free virtual = 49517 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 20005 ; free virtual = 49487 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_016 Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19972 ; free virtual = 49455 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully --------------------------------------------------------------------------------- Start Final Netlist Cleanup INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors --------------------------------------------------------------------------------- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1546.277 ; gain = 0.000 ; free physical = 20005 ; free virtual = 49489 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1546.277 ; gain = 0.000 ; free physical = 19978 ; free virtual = 49462 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19941 ; free virtual = 49425 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19941 ; free virtual = 49425 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19940 ; free virtual = 49424 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19940 ; free virtual = 49424 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19940 ; free virtual = 49424 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19939 ; free virtual = 49423 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19939 ; free virtual = 49423 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 19940 ; free virtual = 49424 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 19940 ; free virtual = 49424 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 20026 ; free virtual = 49512 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement Command: report_drc (run_mandatory_drcs) for: placer_checks WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3753 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1564.855 ; gain = 0.000 ; free physical = 19837 ; free virtual = 49324 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.51 . Memory (MB): peak = 1564.855 ; gain = 0.000 ; free physical = 19819 ; free virtual = 49306 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 19881 ; free virtual = 49369 Loading data files... Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 19660 ; free virtual = 49149 --------------------------------------------------------------------------------- 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 19675 ; free virtual = 49163 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1556.867 ; gain = 0.000 ; free physical = 19518 ; free virtual = 49006 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1556.867 ; gain = 0.000 ; free physical = 19466 ; free virtual = 48955 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 19497 ; free virtual = 48986 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 19494 ; free virtual = 48983 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 19220 ; free virtual = 48711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 19142 ; free virtual = 48633 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 19140 ; free virtual = 48631 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 19122 ; free virtual = 48613 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 19064 ; free virtual = 48555 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 18839 ; free virtual = 48330 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 18822 ; free virtual = 48314 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 18821 ; free virtual = 48312 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 18819 ; free virtual = 48311 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 18817 ; free virtual = 48309 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 18817 ; free virtual = 48309 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 18817 ; free virtual = 48308 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 18637 ; free virtual = 48129 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 18547 ; free virtual = 48039 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Starting Routing Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 104554cdc Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 18579 ; free virtual = 48071 Phase 1.3 Build Placer Netlist Model INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.3 Build Placer Netlist Model | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 18572 ; free virtual = 48065 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 18571 ; free virtual = 48064 Phase 1 Placer Initialization | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 18570 ; free virtual = 48063 Phase 2 Global Placement Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2062.926 ; gain = 43.668 ; free physical = 18414 ; free virtual = 47907 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.914 ; gain = 48.656 ; free physical = 18371 ; free virtual = 47864 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.914 ; gain = 48.656 ; free physical = 18371 ; free virtual = 47864 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Number of Nodes with overlaps = 0 INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2077.969 ; gain = 58.711 ; free physical = 18303 ; free virtual = 47796 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] Phase 3 Initial Routing WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading site data... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 18310 ; free virtual = 47808 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18310 ; free virtual = 47805 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 18309 ; free virtual = 47803 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 18310 ; free virtual = 47805 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 18310 ; free virtual = 47804 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 18310 ; free virtual = 47804 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 18310 ; free virtual = 47804 Phase 7 Route finalize Loading route data... Processing options... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Creating bitmap... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 18299 ; free virtual = 47793 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 18292 ; free virtual = 47786 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18281 ; free virtual = 47775 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18280 ; free virtual = 47774 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 18280 ; free virtual = 47774 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 18316 ; free virtual = 47810 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2121.758 ; gain = 134.516 ; free physical = 18315 ; free virtual = 47810 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18309 ; free virtual = 47804 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 18295 ; free virtual = 47791 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 19390bb85 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18103 ; free virtual = 47598 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19390bb85 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18106 ; free virtual = 47601 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22760be29 Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18115 ; free virtual = 47610 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 2013b9bf4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18104 ; free virtual = 47599 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1caeffc59 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18097 ; free virtual = 47593 Phase 3.5 Small Shape Detail Placement Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4631 Phase 3.5 Small Shape Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18126 ; free virtual = 47621 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18116 ; free virtual = 47612 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18106 ; free virtual = 47601 Phase 3 Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18096 ; free virtual = 47592 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18091 ; free virtual = 47587 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18084 ; free virtual = 47580 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18081 ; free virtual = 47577 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18082 ; free virtual = 47578 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18077 ; free virtual = 47573 Ending Placer Task | Checksum: 1d105b369 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 18079 ; free virtual = 47575 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.551 ; gain = 667.609 ; free physical = 18078 ; free virtual = 47575 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 17930 ; free virtual = 47427 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 17744 ; free virtual = 47241 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17735 ; free virtual = 47232 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec660a5f ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.766 ; gain = 0.000 ; free physical = 17640 ; free virtual = 47138 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17602 ; free virtual = 47100 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17598 ; free virtual = 47095 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17587 ; free virtual = 47085 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17580 ; free virtual = 47078 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17578 ; free virtual = 47076 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17573 ; free virtual = 47071 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17571 ; free virtual = 47069 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 17565 ; free virtual = 47063 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 17566 ; free virtual = 47064 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Creating bitstream... Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.480 ; gain = 457.203 ; free physical = 17351 ; free virtual = 46850 Phase 1.3 Build Placer Netlist Model INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4711 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 16918 ; free virtual = 46418 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 16908 ; free virtual = 46408 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 16875 ; free virtual = 46375 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 16880 ; free virtual = 46380 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17054 ; free virtual = 46558 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17052 ; free virtual = 46556 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17048 ; free virtual = 46552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17047 ; free virtual = 46551 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17044 ; free virtual = 46548 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17043 ; free virtual = 46547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17041 ; free virtual = 46545 Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.480 ; gain = 457.203 ; free physical = 17041 ; free virtual = 46545 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 17038 ; free virtual = 46542 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 17038 ; free virtual = 46542 INFO: [Project 1-571] Translating synthesized netlist Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.480 ; gain = 457.203 ; free physical = 16894 ; free virtual = 46398 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.480 ; gain = 457.203 ; free physical = 16782 ; free virtual = 46287 Phase 2 Global Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.387 ; gain = 487.531 ; free physical = 16648 ; free virtual = 46153 Phase 1.3 Build Placer Netlist Model INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 16491 ; free virtual = 45996 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-570] Preparing netlist for logic optimization 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 16394 ; free virtual = 45900 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 16290 ; free virtual = 45796 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:12:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2461.117 ; gain = 341.105 ; free physical = 16239 ; free virtual = 45745 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:12:40 2019... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Bitstream size: 4243411 bytes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Config size: 1060815 words Number of configuration frames: 9996 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.453 ; gain = 0.000 ; free physical = 17182 ; free virtual = 46688 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 17172 ; free virtual = 46678 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 17171 ; free virtual = 46677 touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.496 ; gain = 517.531 ; free physical = 17153 ; free virtual = 46660 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.496 ; gain = 517.531 ; free physical = 17143 ; free virtual = 46650 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.496 ; gain = 517.531 ; free physical = 17135 ; free virtual = 46642 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.496 ; gain = 517.531 ; free physical = 17121 ; free virtual = 46628 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.496 ; gain = 517.531 ; free physical = 17112 ; free virtual = 46620 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.496 ; gain = 517.531 ; free physical = 17109 ; free virtual = 46616 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.496 ; gain = 583.562 ; free physical = 17107 ; free virtual = 46615 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 17107 ; free virtual = 46614 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 17092 ; free virtual = 46599 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 17072 ; free virtual = 46580 Phase 1.3 Build Placer Netlist Model Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 17049 ; free virtual = 46557 Phase 3.3 Area Swap Optimization Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 17009 ; free virtual = 46517 Phase 3.4 Pipeline Register Optimization Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 487.531 ; free physical = 17009 ; free virtual = 46517 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 487.531 ; free physical = 17058 ; free virtual = 46566 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 17058 ; free virtual = 46566 Phase 3.5 Small Shape Detail Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 487.531 ; free physical = 17055 ; free virtual = 46563 Phase 2 Final Placement Cleanup Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 17053 ; free virtual = 46561 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Final Placement Cleanup | Checksum: 208e4f915 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 487.531 ; free physical = 17052 ; free virtual = 46560 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 487.531 ; free physical = 17048 ; free virtual = 46556 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 17047 ; free virtual = 46555 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:16] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 17011 ; free virtual = 46519 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 16938 ; free virtual = 46447 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 16936 ; free virtual = 46445 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16981 ; free virtual = 46490 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 16964 ; free virtual = 46474 --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16964 ; free virtual = 46474 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16986 ; free virtual = 46499 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16992 ; free virtual = 46508 report_drc (run_mandatory_drcs) completed successfully Phase 4 Post Placement Optimization and Clean-Up INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4.1 Post Commit Optimization Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 16987 ; free virtual = 46497 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 16985 ; free virtual = 46495 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16983 ; free virtual = 46493 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] Phase 4.2 Post Placement Cleanup WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16974 ; free virtual = 46485 Phase 4.3 Placer Reporting Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 16953 ; free virtual = 46464 Phase 1.4 Constrain Clocks/Macros Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16946 ; free virtual = 46456 Phase 4.4 Final Placement Cleanup Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 16945 ; free virtual = 46456 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 16934 ; free virtual = 46445 Phase 2 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16926 ; free virtual = 46437 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 16917 ; free virtual = 46427 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16925 ; free virtual = 46436 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 16941 ; free virtual = 46452 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 16937 ; free virtual = 46448 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.527 ; gain = 553.250 ; free physical = 16936 ; free virtual = 46447 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.527 ; gain = 631.281 ; free physical = 16935 ; free virtual = 46446 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 16836 ; free virtual = 46348 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:16] INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs report_drc (run_mandatory_drcs) completed successfully Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1 Build RT Design Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 16804 ; free virtual = 46317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 16743 ; free virtual = 46257 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 16741 ; free virtual = 46255 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 16702 ; free virtual = 46222 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 16681 ; free virtual = 46202 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 16617 ; free virtual = 46138 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16614 ; free virtual = 46135 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:13:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2460.863 ; gain = 339.105 ; free physical = 16501 ; free virtual = 46022 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:13:00 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16501 ; free virtual = 46022 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16503 ; free virtual = 46024 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16503 ; free virtual = 46025 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16506 ; free virtual = 46028 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16510 ; free virtual = 46031 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16510 ; free virtual = 46031 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16511 ; free virtual = 46033 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 16513 ; free virtual = 46034 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 16509 ; free virtual = 46030 INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 17034 ; free virtual = 46558 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 16942 ; free virtual = 46465 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 16933 ; free virtual = 46457 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16932 ; free virtual = 46456 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 16914 ; free virtual = 46438 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 16913 ; free virtual = 46438 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 16913 ; free virtual = 46438 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 16913 ; free virtual = 46437 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 16920 ; free virtual = 46444 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 16919 ; free virtual = 46443 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 16919 ; free virtual = 46443 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16892 ; free virtual = 46417 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16891 ; free virtual = 46415 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16873 ; free virtual = 46398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16873 ; free virtual = 46397 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16871 ; free virtual = 46396 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16869 ; free virtual = 46394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16868 ; free virtual = 46393 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 16866 ; free virtual = 46391 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 16866 ; free virtual = 46390 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 16448 ; free virtual = 45973 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 16444 ; free virtual = 45969 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 16442 ; free virtual = 45968 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 16442 ; free virtual = 45968 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 16481 ; free virtual = 46006 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 16480 ; free virtual = 46005 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 16480 ; free virtual = 46006 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 16479 ; free virtual = 46005 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 147c14821 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 16438 ; free virtual = 45963 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c14821 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 16410 ; free virtual = 45936 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c14821 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 16410 ; free virtual = 45936 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5977 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 128d436ff Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16402 ; free virtual = 45928 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16350 ; free virtual = 45877 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16336 ; free virtual = 45863 Phase 4 Rip-up And Reroute | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16336 ; free virtual = 45863 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16336 ; free virtual = 45863 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16336 ; free virtual = 45863 Phase 6 Post Hold Fix | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16336 ; free virtual = 45863 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 16350 ; free virtual = 45876 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 16348 ; free virtual = 45875 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 16348 ; free virtual = 45874 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 16379 ; free virtual = 45905 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2111.762 ; gain = 179.516 ; free physical = 16379 ; free virtual = 45905 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing placer database... Starting Routing Task Writing XDEF routing. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2111.762 ; gain = 0.000 ; free physical = 16367 ; free virtual = 45895 Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 16333 ; free virtual = 45861 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1544.949 ; gain = 0.000 ; free physical = 16181 ; free virtual = 45709 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.62 . Memory (MB): peak = 1544.949 ; gain = 0.000 ; free physical = 16193 ; free virtual = 45722 Phase 1 Build RT Design | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 16098 ; free virtual = 45628 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 15983 ; free virtual = 45513 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 15980 ; free virtual = 45510 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 171fe028c Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16019 ; free virtual = 45549 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 16015 ; free virtual = 45545 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16005 ; free virtual = 45536 INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16009 ; free virtual = 45540 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4 Rip-up And Reroute | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16013 ; free virtual = 45543 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16015 ; free virtual = 45545 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16015 ; free virtual = 45546 Phase 6 Post Hold Fix | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16018 ; free virtual = 45548 Phase 7 Route finalize Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16028 ; free virtual = 45559 Phase 8 Verifying routed nets Loading data files... Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16026 ; free virtual = 45557 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16026 ; free virtual = 45556 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.234 ; gain = 10.684 ; free physical = 16062 ; free virtual = 45593 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2142.023 ; gain = 49.473 ; free physical = 16062 ; free virtual = 45593 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2142.023 ; gain = 0.000 ; free physical = 15961 ; free virtual = 45495 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 15851 ; free virtual = 45383 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 15848 ; free virtual = 45380 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 15892 ; free virtual = 45425 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 15787 ; free virtual = 45320 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 15754 ; free virtual = 45288 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 15751 ; free virtual = 45285 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 15710 ; free virtual = 45244 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 6188 Loading site data... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 15018 ; free virtual = 44555 --------------------------------------------------------------------------------- Creating bitstream... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 15011 ; free virtual = 44548 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 15006 ; free virtual = 44543 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14997 ; free virtual = 44535 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14988 ; free virtual = 44525 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14996 ; free virtual = 44534 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14974 ; free virtual = 44511 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14966 ; free virtual = 44503 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14987 ; free virtual = 44525 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14985 ; free virtual = 44522 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 14983 ; free virtual = 44521 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 14985 ; free virtual = 44522 INFO: [Project 1-571] Translating synthesized netlist Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.180 ; gain = 44.668 ; free physical = 14959 ; free virtual = 44497 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.168 ; gain = 50.656 ; free physical = 14927 ; free virtual = 44465 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.168 ; gain = 50.656 ; free physical = 14927 ; free virtual = 44466 Phase 1 Build RT Design | Checksum: 10072c28e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.070 ; gain = 50.668 ; free physical = 14901 ; free virtual = 44439 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2083.473 ; gain = 60.961 ; free physical = 14877 ; free virtual = 44416 Phase 3 Initial Routing INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 14835 ; free virtual = 44373 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 14832 ; free virtual = 44371 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14781 ; free virtual = 44321 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14809 ; free virtual = 44350 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14809 ; free virtual = 44350 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14809 ; free virtual = 44350 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14807 ; free virtual = 44349 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14806 ; free virtual = 44348 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.473 ; gain = 62.961 ; free physical = 14901 ; free virtual = 44443 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.473 ; gain = 65.961 ; free physical = 14890 ; free virtual = 44432 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.473 ; gain = 65.961 ; free physical = 14933 ; free virtual = 44475 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.473 ; gain = 65.961 ; free physical = 14970 ; free virtual = 44512 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2127.262 ; gain = 136.766 ; free physical = 14971 ; free virtual = 44513 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing placer database... Number of Nodes with overlaps = 0 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 2 Router Initialization | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 15047 ; free virtual = 44593 Phase 3 Initial Routing Write XDEF Complete: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2127.262 ; gain = 0.000 ; free physical = 15048 ; free virtual = 44595 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 15005 ; free virtual = 44549 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14962 ; free virtual = 44506 Phase 4 Rip-up And Reroute | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14949 ; free virtual = 44492 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14928 ; free virtual = 44472 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14905 ; free virtual = 44449 Phase 6 Post Hold Fix | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14887 ; free virtual = 44431 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14778 ; free virtual = 44322 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14779 ; free virtual = 44323 Phase 9 Depositing Routes Running DRC as a precondition to command write_bitstream Loading site data... Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 1a3bb806c Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14764 ; free virtual = 44308 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 14805 ; free virtual = 44349 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2217.777 ; gain = 165.391 ; free physical = 14804 ; free virtual = 44348 INFO: [Timing 38-35] Done setting XDC timing constraints. Loading route data... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2128.754 ; gain = 29.227 ; free physical = 14762 ; free virtual = 44307 Processing options... Creating bitmap... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2134.742 ; gain = 35.215 ; free physical = 14699 ; free virtual = 44244 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2134.742 ; gain = 35.215 ; free physical = 14699 ; free virtual = 44244 Writing placer database... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 14682 ; free virtual = 44228 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1cc0cc705 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2134.082 ; gain = 49.668 ; free physical = 14669 ; free virtual = 44217 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 14676 ; free virtual = 44225 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1cc0cc705 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.070 ; gain = 59.656 ; free physical = 14591 ; free virtual = 44142 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1cc0cc705 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.070 ; gain = 59.656 ; free physical = 14587 ; free virtual = 44138 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14579 ; free virtual = 44131 Phase 3 Initial Routing INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:13:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2456.867 ; gain = 345.105 ; free physical = 14570 ; free virtual = 44122 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:13:36 2019... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14566 ; free virtual = 44120 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14561 ; free virtual = 44114 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14561 ; free virtual = 44114 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14561 ; free virtual = 44114 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14561 ; free virtual = 44114 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14561 ; free virtual = 44114 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14660 ; free virtual = 44215 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14660 ; free virtual = 44215 Phase 9 Depositing Routes 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 14667 ; free virtual = 44222 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14668 ; free virtual = 44223 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.797 ; gain = 55.270 ; free physical = 14712 ; free virtual = 44266 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2193.586 ; gain = 94.059 ; free physical = 14720 ; free virtual = 44275 INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 2 Router Initialization | Checksum: 169be60b9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 14716 ; free virtual = 44271 Phase 3 Initial Routing Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Bitstream size: 4243411 bytes WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Number of Nodes with overlaps = 0 touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_017 Phase 3 Initial Routing | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15568 ; free virtual = 45127 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15544 ; free virtual = 45104 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Phase 4 Rip-up And Reroute | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15539 ; free virtual = 45100 Phase 5 Delay and Skew Optimization INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5559] Phase 5 Delay and Skew Optimization | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15531 ; free virtual = 45093 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 6.1 Hold Fix Iter | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15520 ; free virtual = 45082 Phase 6 Post Hold Fix | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15513 ; free virtual = 45076 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 15507 ; free virtual = 45070 Phase 1.3 Build Placer Netlist Model Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15446 ; free virtual = 45011 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15429 ; free virtual = 44993 Phase 9 Depositing Routes report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] Starting Placer Task Phase 9 Depositing Routes | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15446 ; free virtual = 45016 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 15493 ; free virtual = 45062 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2217.789 ; gain = 165.391 ; free physical = 15494 ; free virtual = 45064 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 15496 ; free virtual = 45066 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 15497 ; free virtual = 45066 Writing placer database... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 15502 ; free virtual = 45079 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 15415 ; free virtual = 44997 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 15413 ; free virtual = 44995 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 15248 ; free virtual = 44840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Timing 38-35] Done setting XDC timing constraints. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.777 ; gain = 0.000 ; free physical = 15232 ; free virtual = 44834 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.586 ; gain = 0.000 ; free physical = 15128 ; free virtual = 44743 Loading data files... Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.449 ; gain = 0.000 ; free physical = 15127 ; free virtual = 44743 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2217.777 ; gain = 0.000 ; free physical = 15129 ; free virtual = 44721 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 15027 ; free virtual = 44603 Phase 1.4 Constrain Clocks/Macros WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Running DRC as a precondition to command write_bitstream Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 15065 ; free virtual = 44643 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.789 ; gain = 0.000 ; free physical = 15048 ; free virtual = 44630 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 15035 ; free virtual = 44617 Phase 2 Global Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2004.164 ; gain = 456.203 ; free physical = 15029 ; free virtual = 44611 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.789 ; gain = 0.000 ; free physical = 14909 ; free virtual = 44467 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15110 ; free virtual = 44674 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.164 ; gain = 456.203 ; free physical = 15116 ; free virtual = 44680 Phase 1.4 Constrain Clocks/Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15107 ; free virtual = 44671 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.164 ; gain = 456.203 ; free physical = 15115 ; free virtual = 44678 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.164 ; gain = 456.203 ; free physical = 15110 ; free virtual = 44674 Phase 2 Global Placement Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15061 ; free virtual = 44624 Phase 3.3 Area Swap Optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15089 ; free virtual = 44654 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15055 ; free virtual = 44620 Phase 3.5 Small Shape Detail Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:13:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 15007 ; free virtual = 44571 --------------------------------------------------------------------------------- 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.129 ; gain = 333.105 ; free physical = 15011 ; free virtual = 44575 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:13:49 2019... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 15108 ; free virtual = 44672 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15308 ; free virtual = 44872 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15926 ; free virtual = 45492 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15884 ; free virtual = 45450 Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15884 ; free virtual = 45450 --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15879 ; free virtual = 45445 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15876 ; free virtual = 45441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15871 ; free virtual = 45437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15870 ; free virtual = 45436 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15871 ; free virtual = 45437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15867 ; free virtual = 45433 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.215 ; free physical = 15859 ; free virtual = 45425 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.215 ; free physical = 15859 ; free virtual = 45425 INFO: [Project 1-571] Translating synthesized netlist Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15831 ; free virtual = 45397 Phase 1 Build RT Design | Checksum: 18a962264 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.953 ; gain = 41.668 ; free physical = 15810 ; free virtual = 45375 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 3 Detail Placement | Checksum: 181723f81 Phase 2.1 Fix Topology Constraints Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15763 ; free virtual = 45329 Phase 2.1 Fix Topology Constraints | Checksum: 18a962264 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 15762 ; free virtual = 45328 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18a962264 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 15759 ; free virtual = 45325 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15749 ; free virtual = 45315 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15709 ; free virtual = 45276 Phase 4.2 Post Placement Cleanup Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15701 ; free virtual = 45268 Phase 3.2 Commit Most Macros & LUTRAMs Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15743 ; free virtual = 45309 Phase 4.3 Placer Reporting WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10fb680fc Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.371 ; gain = 61.086 ; free physical = 15671 ; free virtual = 45237 Phase 3 Initial Routing Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15671 ; free virtual = 45238 Phase 4.4 Final Placement Cleanup Loading site data... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15687 ; free virtual = 45253 Phase 3.3 Area Swap Optimization Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15620 ; free virtual = 45186 Loading route data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 15541 ; free virtual = 45108 Processing options... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Creating bitmap... Phase 4.1 Global Iteration 0 | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 15603 ; free virtual = 45170 Phase 4 Rip-up And Reroute | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 15606 ; free virtual = 45173 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 15611 ; free virtual = 45177 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 15616 ; free virtual = 45183 Phase 6 Post Hold Fix | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 15617 ; free virtual = 45184 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15617 ; free virtual = 45184 Phase 7 Route finalize Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15643 ; free virtual = 45210 Phase 3.4 Pipeline Register Optimization Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 15595 ; free virtual = 45162 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 631.953 ; free physical = 15598 ; free virtual = 45165 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 7 Route finalize | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 15597 ; free virtual = 45164 Phase 8 Verifying routed nets Verification completed successfully INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 8 Verifying routed nets | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 15605 ; free virtual = 45171 Phase 9 Depositing Routes Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15575 ; free virtual = 45142 Phase 3.5 Small Shape Detail Placement Phase 9 Depositing Routes | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 15564 ; free virtual = 45131 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 15602 ; free virtual = 45169 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2130.160 ; gain = 135.891 ; free physical = 15601 ; free virtual = 45168 Writing placer database... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2130.160 ; gain = 0.000 ; free physical = 15569 ; free virtual = 45139 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15506 ; free virtual = 45074 Phase 3.6 Re-assign LUT pins Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 15e82b8af Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2063.930 ; gain = 44.668 ; free physical = 15530 ; free virtual = 45099 Phase 1 Build RT Design Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.918 ; gain = 49.656 ; free physical = 15474 ; free virtual = 45042 Phase 2.2 Pre Route Cleanup Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15473 ; free virtual = 45041 Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.918 ; gain = 49.656 ; free physical = 15476 ; free virtual = 45045 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15411 ; free virtual = 44980 Loading data files... Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2078.973 ; gain = 59.711 ; free physical = 15370 ; free virtual = 44938 Phase 3 Initial Routing Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15370 ; free virtual = 44939 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15312 ; free virtual = 44881 Phase 4.2 Post Placement Cleanup Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 15314 ; free virtual = 44884 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 15304 ; free virtual = 44874 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 15304 ; free virtual = 44873 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 15303 ; free virtual = 44872 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 15302 ; free virtual = 44871 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 15301 ; free virtual = 44870 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15272 ; free virtual = 44841 Phase 4.3 Placer Reporting Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 15272 ; free virtual = 44842 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2083.973 ; gain = 64.711 ; free physical = 15278 ; free virtual = 44847 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2083.973 ; gain = 64.711 ; free physical = 15274 ; free virtual = 44843 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2083.973 ; gain = 64.711 ; free physical = 15309 ; free virtual = 44878 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2122.762 ; gain = 135.516 ; free physical = 15308 ; free virtual = 44877 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15311 ; free virtual = 44880 Phase 4.4 Final Placement Cleanup Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2122.762 ; gain = 0.000 ; free physical = 15277 ; free virtual = 44849 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15257 ; free virtual = 44829 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15178 ; free virtual = 44748 Loading data files... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.207 ; gain = 544.246 ; free physical = 15085 ; free virtual = 44655 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.207 ; gain = 624.949 ; free physical = 15081 ; free virtual = 44651 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.703 ; gain = 333.812 ; free physical = 14963 ; free virtual = 44538 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 14971 ; free virtual = 44546 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1482.734 ; gain = 0.000 ; free physical = 14800 ; free virtual = 44376 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1482.734 ; gain = 0.000 ; free physical = 14799 ; free virtual = 44374 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 14799 ; free virtual = 44374 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 14798 ; free virtual = 44373 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 14797 ; free virtual = 44373 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 14797 ; free virtual = 44373 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 14797 ; free virtual = 44373 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 14798 ; free virtual = 44374 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 14789 ; free virtual = 44365 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:14:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2461.438 ; gain = 334.176 ; free physical = 14731 ; free virtual = 44307 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:14:01 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8317 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:14:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.691 ; gain = 339.105 ; free physical = 15014 ; free virtual = 44599 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:14:09 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_018 Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8522 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 15645 ; free virtual = 45235 --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Creating bitstream... Creating bitstream... Creating bitstream... WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:16] Writing bitstream ./design.bit... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.223 ; gain = 0.000 ; free physical = 15439 ; free virtual = 45040 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 15436 ; free virtual = 45038 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.266 ; gain = 510.531 ; free physical = 15428 ; free virtual = 45030 Phase 1.3 Build Placer Netlist Model Writing bitstream ./design.bit... Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.266 ; gain = 510.531 ; free physical = 15438 ; free virtual = 45041 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.266 ; gain = 510.531 ; free physical = 15440 ; free virtual = 45044 Writing bitstream ./design.bit... Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.266 ; gain = 510.531 ; free physical = 15436 ; free virtual = 45043 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.266 ; gain = 510.531 ; free physical = 15426 ; free virtual = 45040 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.266 ; gain = 510.531 ; free physical = 15444 ; free virtual = 45059 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 1993.266 ; gain = 576.562 ; free physical = 15446 ; free virtual = 45061 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 15656 ; free virtual = 45266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 15716 ; free virtual = 45326 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 15911 ; free virtual = 45525 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:14:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:49 . Memory (MB): peak = 2607.938 ; gain = 390.160 ; free physical = 16141 ; free virtual = 45757 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 16143 ; free virtual = 45758 --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:14:30 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:14:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Config size: 1060815 words Number of configuration frames: 9996 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2469.266 ; gain = 339.105 ; free physical = 17312 ; free virtual = 46928 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:14:30 2019... DONE ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_019 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 18307 ; free virtual = 47925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 18283 ; free virtual = 47901 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 18280 ; free virtual = 47899 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_020 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 18229 ; free virtual = 47848 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:14:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:48 . Memory (MB): peak = 2606.910 ; gain = 389.121 ; free physical = 18179 ; free virtual = 47798 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:14:32 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8912 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:14:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2460.867 ; gain = 338.105 ; free physical = 19303 ; free virtual = 48923 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:14:32 2019... touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 21992 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 20144 ; free virtual = 49778 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 20106 ; free virtual = 49740 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20038 ; free virtual = 49673 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19965 ; free virtual = 49601 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19962 ; free virtual = 49598 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19955 ; free virtual = 49591 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19955 ; free virtual = 49591 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19954 ; free virtual = 49590 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19954 ; free virtual = 49590 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19954 ; free virtual = 49590 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 19953 ; free virtual = 49589 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 19954 ; free virtual = 49591 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9199 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1332.930 ; gain = 237.480 ; free physical = 19839 ; free virtual = 49477 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1332.930 ; gain = 237.480 ; free physical = 19822 ; free virtual = 49460 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19815 ; free virtual = 49453 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19749 ; free virtual = 49388 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19748 ; free virtual = 49386 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19746 ; free virtual = 49385 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19746 ; free virtual = 49385 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19745 ; free virtual = 49384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19745 ; free virtual = 49384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19745 ; free virtual = 49384 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 19745 ; free virtual = 49383 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.953 ; gain = 246.496 ; free physical = 19747 ; free virtual = 49386 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 19720 ; free virtual = 49359 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 19450 ; free virtual = 49091 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 19560 ; free virtual = 49200 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 19559 ; free virtual = 49199 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 19538 ; free virtual = 49179 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2129.957 ; gain = 30.758 ; free physical = 19427 ; free virtual = 49068 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2135.945 ; gain = 36.746 ; free physical = 19349 ; free virtual = 48990 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2135.945 ; gain = 36.746 ; free physical = 19348 ; free virtual = 48988 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19293 ; free virtual = 48934 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19355 ; free virtual = 48997 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19351 ; free virtual = 48993 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19351 ; free virtual = 48993 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19351 ; free virtual = 48992 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19350 ; free virtual = 48992 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19350 ; free virtual = 48992 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19324 ; free virtual = 48965 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19322 ; free virtual = 48964 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19318 ; free virtual = 48960 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.000 ; gain = 54.801 ; free physical = 19351 ; free virtual = 48992 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:53 . Memory (MB): peak = 2192.789 ; gain = 93.590 ; free physical = 19350 ; free virtual = 48991 Writing placer database... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.969 ; gain = 36.762 ; free physical = 19236 ; free virtual = 48887 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.957 ; gain = 43.750 ; free physical = 19190 ; free virtual = 48842 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.957 ; gain = 43.750 ; free physical = 19190 ; free virtual = 48842 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.945 ; gain = 342.055 ; free physical = 19219 ; free virtual = 48872 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 19210 ; free virtual = 48863 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19167 ; free virtual = 48823 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19146 ; free virtual = 48805 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19142 ; free virtual = 48802 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19142 ; free virtual = 48802 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19142 ; free virtual = 48802 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19141 ; free virtual = 48801 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19142 ; free virtual = 48802 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19113 ; free virtual = 48774 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19109 ; free virtual = 48770 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19107 ; free virtual = 48769 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.012 ; gain = 62.805 ; free physical = 19143 ; free virtual = 48805 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2193.801 ; gain = 101.594 ; free physical = 19146 ; free virtual = 48808 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Writing placer database... Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.977 ; gain = 0.000 ; free physical = 19140 ; free virtual = 48803 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 165c53615 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1488.977 ; gain = 0.000 ; free physical = 19137 ; free virtual = 48800 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 19141 ; free virtual = 48811 Writing XDEF routing. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.789 ; gain = 0.000 ; free physical = 19133 ; free virtual = 48804 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] Command: report_drc (run_mandatory_drcs) for: placer_checks WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1548.281 ; gain = 0.000 ; free physical = 19032 ; free virtual = 48693 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 147c036e4 Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 19012 ; free virtual = 48674 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1548.281 ; gain = 0.000 ; free physical = 18975 ; free virtual = 48639 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c036e4 Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 18971 ; free virtual = 48634 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c036e4 Time (s): cpu = 00:00:39 ; elapsed = 00:00:48 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 18970 ; free virtual = 48634 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 161e7cd46 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 18900 ; free virtual = 48566 Phase 3 Initial Routing ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.801 ; gain = 0.000 ; free physical = 18883 ; free virtual = 48552 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 18890 ; free virtual = 48559 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 18893 ; free virtual = 48566 Phase 4 Rip-up And Reroute | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 18894 ; free virtual = 48566 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 18893 ; free virtual = 48565 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 18894 ; free virtual = 48567 Phase 6 Post Hold Fix | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 18895 ; free virtual = 48567 Phase 7 Route finalize Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 18894 ; free virtual = 48565 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 18893 ; free virtual = 48564 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 18893 ; free virtual = 48563 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 18927 ; free virtual = 48598 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 18928 ; free virtual = 48598 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 18907 ; free virtual = 48580 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 18907 ; free virtual = 48580 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 18921 ; free virtual = 48570 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18892 ; free virtual = 48542 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:16] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:7] Running DRC as a precondition to command write_bitstream INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18807 ; free virtual = 48464 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18804 ; free virtual = 48461 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18797 ; free virtual = 48454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18792 ; free virtual = 48449 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18780 ; free virtual = 48437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18780 ; free virtual = 48437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18769 ; free virtual = 48426 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18764 ; free virtual = 48421 INFO: Launching helper process for spawning children vivado processes Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 18762 ; free virtual = 48419 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 18763 ; free virtual = 48414 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 9418 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9455 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 18713 ; free virtual = 48364 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 18710 ; free virtual = 48361 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9498 Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 18199 ; free virtual = 47853 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9536 Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 17933 ; free virtual = 47588 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 17744 ; free virtual = 47400 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 17726 ; free virtual = 47382 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 17593 ; free virtual = 47250 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 17578 ; free virtual = 47236 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 17515 ; free virtual = 47173 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17518 ; free virtual = 47176 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 17511 ; free virtual = 47169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17363 ; free virtual = 47022 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17349 ; free virtual = 47008 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17321 ; free virtual = 46980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17316 ; free virtual = 46976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17307 ; free virtual = 46966 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17298 ; free virtual = 46957 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17292 ; free virtual = 46952 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 17270 ; free virtual = 46930 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 17261 ; free virtual = 46921 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 17196 ; free virtual = 46856 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1909.465 ; gain = 0.000 ; free physical = 16654 ; free virtual = 46317 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 16624 ; free virtual = 46288 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e0a71f46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1997.508 ; gain = 508.531 ; free physical = 16497 ; free virtual = 46162 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1997.508 ; gain = 508.531 ; free physical = 16491 ; free virtual = 46156 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1997.508 ; gain = 508.531 ; free physical = 16483 ; free virtual = 46147 Phase 1 Placer Initialization | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1997.508 ; gain = 508.531 ; free physical = 16474 ; free virtual = 46138 Phase 2 Global Placement Creating bitstream... WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:16] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:16] Loading site data... WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:7] Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 16122 ; free virtual = 45795 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 16107 ; free virtual = 45774 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2066.949 ; gain = 41.668 ; free physical = 16065 ; free virtual = 45745 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 16066 ; free virtual = 45740 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 16054 ; free virtual = 45722 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 16051 ; free virtual = 45720 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 16046 ; free virtual = 45715 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.938 ; gain = 48.656 ; free physical = 16037 ; free virtual = 45705 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.938 ; gain = 48.656 ; free physical = 16037 ; free virtual = 45705 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.770 ; gain = 0.000 ; free physical = 15993 ; free virtual = 45662 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10276a5af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.367 ; gain = 61.086 ; free physical = 15975 ; free virtual = 45644 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.367 ; gain = 61.086 ; free physical = 16005 ; free virtual = 45678 Creating bitstream... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.367 ; gain = 61.086 ; free physical = 16070 ; free virtual = 45743 Phase 4 Rip-up And Reroute | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.367 ; gain = 61.086 ; free physical = 16107 ; free virtual = 45781 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.367 ; gain = 61.086 ; free physical = 16135 ; free virtual = 45808 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.367 ; gain = 61.086 ; free physical = 16141 ; free virtual = 45814 Phase 6 Post Hold Fix | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.367 ; gain = 61.086 ; free physical = 16141 ; free virtual = 45814 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2087.367 ; gain = 62.086 ; free physical = 16179 ; free virtual = 45852 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.367 ; gain = 64.086 ; free physical = 16176 ; free virtual = 45850 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.367 ; gain = 65.086 ; free physical = 16170 ; free virtual = 45843 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.367 ; gain = 65.086 ; free physical = 16206 ; free virtual = 45879 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2129.156 ; gain = 135.891 ; free physical = 16183 ; free virtual = 45856 Phase 2 Global Placement | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16182 ; free virtual = 45856 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16177 ; free virtual = 45851 Phase 3.2 Commit Most Macros & LUTRAMs Writing placer database... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2433660c9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16176 ; free virtual = 45850 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d113e94 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16161 ; free virtual = 45836 Phase 3.4 Pipeline Register Optimization Writing XDEF routing. Phase 3.4 Pipeline Register Optimization | Checksum: 1e6c59ef9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16187 ; free virtual = 45863 Phase 3.5 Small Shape Detail Placement Writing bitstream ./design.bit... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2129.156 ; gain = 0.000 ; free physical = 16180 ; free virtual = 45857 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.484 ; gain = 455.203 ; free physical = 16401 ; free virtual = 46079 Phase 1.3 Build Placer Netlist Model Phase 3.5 Small Shape Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16491 ; free virtual = 46169 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16504 ; free virtual = 46182 Phase 3.7 Pipeline Register Optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. Phase 3.7 Pipeline Register Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16521 ; free virtual = 46200 INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3 Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16519 ; free virtual = 46198 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16508 ; free virtual = 46186 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16502 ; free virtual = 46181 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16499 ; free virtual = 46178 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16489 ; free virtual = 46167 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16482 ; free virtual = 46161 Ending Placer Task | Checksum: 1d0f627a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.555 ; gain = 604.578 ; free physical = 16487 ; free virtual = 46166 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2093.555 ; gain = 668.609 ; free physical = 16486 ; free virtual = 46165 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 16487 ; free virtual = 46166 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 16486 ; free virtual = 46166 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec567e97 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:15:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2531.895 ; gain = 339.105 ; free physical = 16737 ; free virtual = 46422 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:15:15 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 16868 ; free virtual = 46552 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:15:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.871 ; gain = 343.105 ; free physical = 17723 ; free virtual = 47409 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:15:16 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.484 ; gain = 455.203 ; free physical = 17719 ; free virtual = 47405 Phase 1.4 Constrain Clocks/Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.484 ; gain = 455.203 ; free physical = 17763 ; free virtual = 47448 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 18479 ; free virtual = 48165 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.484 ; gain = 455.203 ; free physical = 18662 ; free virtual = 48348 Phase 2 Global Placement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.39 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 18664 ; free virtual = 48355 touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:15:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2532.906 ; gain = 339.105 ; free physical = 18526 ; free virtual = 48218 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:15:18 2019... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 18575 ; free virtual = 48267 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 19433 ; free virtual = 49125 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 19380 ; free virtual = 49071 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- DONE Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 19306 ; free virtual = 48998 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- touch build/specimen_016/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19133 ; free virtual = 48826 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19152 ; free virtual = 48845 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19155 ; free virtual = 48848 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19195 ; free virtual = 48890 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 19172 ; free virtual = 48875 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19192 ; free virtual = 48905 Phase 3.3 Area Swap Optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 19187 ; free virtual = 48901 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 19155 ; free virtual = 48870 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 19163 ; free virtual = 48877 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19160 ; free virtual = 48874 Phase 3.4 Pipeline Register Optimization --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 19156 ; free virtual = 48870 Phase 2 Final Placement Cleanup Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19153 ; free virtual = 48868 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19140 ; free virtual = 48855 --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 19138 ; free virtual = 48853 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1325.078 ; gain = 229.156 ; free physical = 19159 ; free virtual = 48855 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19159 ; free virtual = 48854 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19158 ; free virtual = 48853 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 19145 ; free virtual = 48840 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 19142 ; free virtual = 48838 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19147 ; free virtual = 48842 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: router_checks --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19146 ; free virtual = 48842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19144 ; free virtual = 48840 --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a --------------------------------------------------------------------------------- Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19144 ; free virtual = 48840 Phase 3.5 Small Shape Detail Placement Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19144 ; free virtual = 48840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19141 ; free virtual = 48836 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19140 ; free virtual = 48836 Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19140 ; free virtual = 48836 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: --------------------------------------------------------------------------------- +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Start Renaming Generated Nets |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | --------------------------------------------------------------------------------- +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19139 ; free virtual = 48835 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19139 ; free virtual = 48834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19138 ; free virtual = 48833 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 19138 ; free virtual = 48833 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 19134 ; free virtual = 48830 Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 19135 ; free virtual = 48831 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.590 ; gain = 269.961 ; free physical = 19137 ; free virtual = 48832 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1325.078 ; gain = 229.156 ; free physical = 19029 ; free virtual = 48746 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1333.105 ; gain = 237.184 ; free physical = 19029 ; free virtual = 48746 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 19047 ; free virtual = 48746 --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19049 ; free virtual = 48748 Phase 3.6 Re-assign LUT pins INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19030 ; free virtual = 48729 Phase 3.7 Pipeline Register Optimization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 19040 ; free virtual = 48739 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 18975 ; free virtual = 48694 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 18939 ; free virtual = 48659 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 18916 ; free virtual = 48635 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 18882 ; free virtual = 48602 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 18894 ; free virtual = 48594 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 18895 ; free virtual = 48595 --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 18895 ; free virtual = 48595 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 18895 ; free virtual = 48596 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.527 ; gain = 543.246 ; free physical = 18856 ; free virtual = 48557 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.527 ; gain = 624.277 ; free physical = 18856 ; free virtual = 48557 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1341.074 ; gain = 245.152 ; free physical = 18240 ; free virtual = 47943 --------------------------------------------------------------------------------- Processing options... Creating bitmap... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 18291 ; free virtual = 47995 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1351.105 ; gain = 255.184 ; free physical = 18036 ; free virtual = 47742 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 18049 ; free virtual = 47755 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1351.105 ; gain = 255.184 ; free physical = 18054 ; free virtual = 47761 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.254 ; gain = 384.359 ; free physical = 18006 ; free virtual = 47713 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 17985 ; free virtual = 47692 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 17871 ; free virtual = 47579 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:42 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17888 ; free virtual = 47595 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1531.289 ; gain = 0.000 ; free physical = 17786 ; free virtual = 47494 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.63 . Memory (MB): peak = 1531.289 ; gain = 0.000 ; free physical = 17698 ; free virtual = 47406 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1546.957 ; gain = 0.000 ; free physical = 17638 ; free virtual = 47346 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.59 . Memory (MB): peak = 1546.957 ; gain = 0.000 ; free physical = 17600 ; free virtual = 47309 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17603 ; free virtual = 47312 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17593 ; free virtual = 47301 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17636 ; free virtual = 47344 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 17635 ; free virtual = 47343 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17624 ; free virtual = 47332 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17620 ; free virtual = 47330 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17619 ; free virtual = 47328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17610 ; free virtual = 47319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17608 ; free virtual = 47318 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.082 ; gain = 263.160 ; free physical = 17607 ; free virtual = 47316 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.090 ; gain = 263.160 ; free physical = 17610 ; free virtual = 47319 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17550 ; free virtual = 47260 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17556 ; free virtual = 47266 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17542 ; free virtual = 47251 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17535 ; free virtual = 47245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17531 ; free virtual = 47241 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17528 ; free virtual = 47238 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17527 ; free virtual = 47238 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 17526 ; free virtual = 47236 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 17527 ; free virtual = 47237 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 17520 ; free virtual = 47230 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11603 Writing bitstream ./design.bit... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11639 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 17620 ; free virtual = 47337 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 17613 ; free virtual = 47330 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 17598 ; free virtual = 47315 Phase 2 Global Placement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11919 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:15:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2468.262 ; gain = 339.105 ; free physical = 17522 ; free virtual = 47241 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:15:46 2019... INFO: [Project 1-570] Preparing netlist for logic optimization Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18462 ; free virtual = 48183 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18439 ; free virtual = 48160 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18350 ; free virtual = 48071 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18372 ; free virtual = 48094 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18359 ; free virtual = 48081 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 18184 ; free virtual = 47906 --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18171 ; free virtual = 47894 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18162 ; free virtual = 47885 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18154 ; free virtual = 47877 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18147 ; free virtual = 47870 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18135 ; free virtual = 47858 Phase 4.2 Post Placement Cleanup INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18101 ; free virtual = 47824 Phase 4.3 Placer Reporting INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 18105 ; free virtual = 47829 --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18119 ; free virtual = 47843 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 18129 ; free virtual = 47853 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 18122 ; free virtual = 47846 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 18121 ; free virtual = 47845 --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18121 ; free virtual = 47845 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 18119 ; free virtual = 47843 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18111 ; free virtual = 47836 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18109 ; free virtual = 47833 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 18109 ; free virtual = 47833 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 17985 ; free virtual = 47711 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 17685 ; free virtual = 47411 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 17528 ; free virtual = 47254 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 17521 ; free virtual = 47247 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 17403 ; free virtual = 47131 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2093.555 ; gain = 0.000 ; free physical = 17299 ; free virtual = 47027 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2093.555 ; gain = 0.000 ; free physical = 17228 ; free virtual = 46955 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2093.555 ; gain = 0.000 ; free physical = 17227 ; free virtual = 46954 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.445 ; gain = 0.000 ; free physical = 17172 ; free virtual = 46899 Phase 2 Router Initialization | Checksum: 174384e93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17172 ; free virtual = 46899 Phase 3 Initial Routing Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.777 ; gain = 0.000 ; free physical = 17178 ; free virtual = 46905 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17133 ; free virtual = 46861 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17132 ; free virtual = 46860 Phase 4 Rip-up And Reroute | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17132 ; free virtual = 46860 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17132 ; free virtual = 46860 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17131 ; free virtual = 46859 Phase 6 Post Hold Fix | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17131 ; free virtual = 46859 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17118 ; free virtual = 46846 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17116 ; free virtual = 46844 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17109 ; free virtual = 46837 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.238 ; gain = 8.684 ; free physical = 17145 ; free virtual = 46873 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2141.027 ; gain = 47.473 ; free physical = 17145 ; free virtual = 46873 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.40 . Memory (MB): peak = 2141.027 ; gain = 0.000 ; free physical = 17071 ; free virtual = 46801 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.492 ; gain = 472.203 ; free physical = 17045 ; free virtual = 46774 Phase 1.3 Build Placer Netlist Model WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2004.160 ; gain = 457.203 ; free physical = 17102 ; free virtual = 46831 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 17025 ; free virtual = 46756 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 16979 ; free virtual = 46709 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16963 ; free virtual = 46694 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16974 ; free virtual = 46705 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16973 ; free virtual = 46704 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16967 ; free virtual = 46698 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16966 ; free virtual = 46697 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16965 ; free virtual = 46696 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16964 ; free virtual = 46695 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16963 ; free virtual = 46693 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 16959 ; free virtual = 46690 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 16960 ; free virtual = 46691 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.492 ; gain = 472.203 ; free physical = 16858 ; free virtual = 46590 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.160 ; gain = 457.203 ; free physical = 16845 ; free virtual = 46577 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.492 ; gain = 472.203 ; free physical = 16872 ; free virtual = 46603 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 16899 ; free virtual = 46630 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:09 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 16911 ; free virtual = 46643 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.160 ; gain = 457.203 ; free physical = 16886 ; free virtual = 46617 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.492 ; gain = 472.203 ; free physical = 16878 ; free virtual = 46610 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.160 ; gain = 457.203 ; free physical = 16877 ; free virtual = 46608 Phase 2 Global Placement INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 16735 ; free virtual = 46467 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 16738 ; free virtual = 46470 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16722 ; free virtual = 46454 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16707 ; free virtual = 46440 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16709 ; free virtual = 46442 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16708 ; free virtual = 46441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16708 ; free virtual = 46441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16707 ; free virtual = 46440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16707 ; free virtual = 46440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16706 ; free virtual = 46440 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 16705 ; free virtual = 46438 Starting Placer Task Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 16707 ; free virtual = 46440 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Project 1-571] Translating synthesized netlist Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1549.863 ; gain = 0.000 ; free physical = 16672 ; free virtual = 46406 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1556.859 ; gain = 0.000 ; free physical = 16650 ; free virtual = 46384 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1549.863 ; gain = 0.000 ; free physical = 16633 ; free virtual = 46366 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1556.859 ; gain = 0.000 ; free physical = 16602 ; free virtual = 46336 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.172 ; gain = 42.668 ; free physical = 16500 ; free virtual = 46235 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 16465 ; free virtual = 46200 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 16465 ; free virtual = 46199 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16457 ; free virtual = 46191 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16503 ; free virtual = 46238 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16518 ; free virtual = 46252 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.465 ; gain = 59.961 ; free physical = 16516 ; free virtual = 46251 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 16535 ; free virtual = 46275 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16523 ; free virtual = 46265 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16512 ; free virtual = 46258 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 16507 ; free virtual = 46256 Phase 3.3 Area Swap Optimization Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 16502 ; free virtual = 46253 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 16501 ; free virtual = 46252 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 16501 ; free virtual = 46252 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 16500 ; free virtual = 46251 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 16500 ; free virtual = 46251 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16485 ; free virtual = 46240 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 3.3 Area Swap Optimization Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 16481 ; free virtual = 46236 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 16480 ; free virtual = 46236 Phase 9 Depositing Routes Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16476 ; free virtual = 46232 Phase 3.4 Pipeline Register Optimization Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 16473 ; free virtual = 46229 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 16511 ; free virtual = 46267 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2127.254 ; gain = 135.766 ; free physical = 16511 ; free virtual = 46268 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16497 ; free virtual = 46253 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Phase 3.4 Pipeline Register Optimization Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16497 ; free virtual = 46253 Phase 3.5 Small Shape Detail Placement Writing placer database... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 16521 ; free virtual = 46258 --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16518 ; free virtual = 46256 Phase 3.5 Small Shape Detail Placement Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 16566 ; free virtual = 46306 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 16534 ; free virtual = 46291 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 16533 ; free virtual = 46291 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 16483 ; free virtual = 46221 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 16475 ; free virtual = 46214 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16491 ; free virtual = 46230 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16445 ; free virtual = 46184 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16425 ; free virtual = 46164 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16411 ; free virtual = 46151 Phase 3.6 Re-assign LUT pins Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16398 ; free virtual = 46137 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16388 ; free virtual = 46127 Phase 3.7 Pipeline Register Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16378 ; free virtual = 46117 Phase 4.2 Post Placement Cleanup Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16356 ; free virtual = 46095 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16348 ; free virtual = 46088 Phase 4.3 Placer Reporting Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16319 ; free virtual = 46059 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16286 ; free virtual = 46026 Phase 4.4 Final Placement Cleanup INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 16314 ; free virtual = 46054 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16311 ; free virtual = 46051 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16309 ; free virtual = 46048 Phase 4.2 Post Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16300 ; free virtual = 46040 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16322 ; free virtual = 46062 Phase 4.3 Placer Reporting WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.539 ; gain = 568.250 ; free physical = 16330 ; free virtual = 46071 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.539 ; gain = 632.281 ; free physical = 16329 ; free virtual = 46070 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14165 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2129.289 ; gain = 37.762 ; free physical = 16310 ; free virtual = 46050 Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16298 ; free virtual = 46038 Phase 4.4 Final Placement Cleanup Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.277 ; gain = 43.750 ; free physical = 16252 ; free virtual = 45993 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.277 ; gain = 43.750 ; free physical = 16252 ; free virtual = 45993 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16190 ; free virtual = 45930 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16163 ; free virtual = 45904 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16165 ; free virtual = 45906 Phase 3 Initial Routing Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2108.211 ; gain = 561.254 ; free physical = 16133 ; free virtual = 45874 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.211 ; gain = 640.957 ; free physical = 16132 ; free virtual = 45872 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 16136 ; free virtual = 45877 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 16136 ; free virtual = 45877 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16133 ; free virtual = 45874 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16135 ; free virtual = 45876 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16135 ; free virtual = 45876 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16135 ; free virtual = 45876 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16134 ; free virtual = 45875 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16134 ; free virtual = 45875 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16103 ; free virtual = 45844 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16103 ; free virtual = 45844 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16097 ; free virtual = 45838 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 16132 ; free virtual = 45873 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2193.121 ; gain = 101.594 ; free physical = 16129 ; free virtual = 45870 Writing placer database... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Loading site data... Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading data files... Loading route data... Processing options... Creating bitmap... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1356.074 ; gain = 260.152 ; free physical = 15902 ; free virtual = 45658 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.121 ; gain = 0.000 ; free physical = 15808 ; free virtual = 45574 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.121 ; gain = 0.000 ; free physical = 15802 ; free virtual = 45547 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1364.105 ; gain = 268.184 ; free physical = 15725 ; free virtual = 45471 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1364.105 ; gain = 268.184 ; free physical = 15702 ; free virtual = 45448 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15600 ; free virtual = 45347 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 15509 ; free virtual = 45257 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15393 ; free virtual = 45140 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15399 ; free virtual = 45147 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15361 ; free virtual = 45109 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15358 ; free virtual = 45106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15342 ; free virtual = 45090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15338 ; free virtual = 45086 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15335 ; free virtual = 45084 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1372.082 ; gain = 276.160 ; free physical = 15330 ; free virtual = 45078 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1372.090 ; gain = 276.160 ; free physical = 15325 ; free virtual = 45074 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 15107 ; free virtual = 44862 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 15087 ; free virtual = 44842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 15082 ; free virtual = 44837 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. Loading route data... Loading data files... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 14830 ; free virtual = 44585 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 14701 ; free virtual = 44457 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 14473 ; free virtual = 44229 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:16:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 14325 ; free virtual = 44081 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2475.133 ; gain = 334.105 ; free physical = 14335 ; free virtual = 44092 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:16:30 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 15333 ; free virtual = 45090 Phase 1.3 Build Placer Netlist Model touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 15305 ; free virtual = 45063 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 15304 ; free virtual = 45062 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 15304 ; free virtual = 45061 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 15303 ; free virtual = 45061 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 15303 ; free virtual = 45061 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 15306 ; free virtual = 45063 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 15306 ; free virtual = 45063 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 22337 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 15259 ; free virtual = 45018 Phase 1.3 Build Placer Netlist Model INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 15187 ; free virtual = 44959 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 15178 ; free virtual = 44947 Phase 1.4 Constrain Clocks/Macros No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 15173 ; free virtual = 44942 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 15160 ; free virtual = 44929 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 15134 ; free virtual = 44903 Phase 2 Final Placement Cleanup Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 15129 ; free virtual = 44898 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15114 ; free virtual = 44883 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 15111 ; free virtual = 44881 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 15119 ; free virtual = 44888 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 15118 ; free virtual = 44888 Phase 1.4 Constrain Clocks/Macros Ending Placer Task | Checksum: 110ed1b10 Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 15119 ; free virtual = 44889 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 15119 ; free virtual = 44889 Phase 2 Final Placement Cleanup Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 15119 ; free virtual = 44889 Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 15119 ; free virtual = 44889 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 15121 ; free virtual = 44890 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 15121 ; free virtual = 44890 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 15119 ; free virtual = 44889 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 15085 ; free virtual = 44855 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 15033 ; free virtual = 44803 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15018 ; free virtual = 44788 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15008 ; free virtual = 44778 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15005 ; free virtual = 44776 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15005 ; free virtual = 44775 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15004 ; free virtual = 44774 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15004 ; free virtual = 44774 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15004 ; free virtual = 44774 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 14994 ; free virtual = 44764 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 14994 ; free virtual = 44764 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 14992 ; free virtual = 44762 Phase 2 Final Placement Cleanup INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:16:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2470.359 ; gain = 343.105 ; free physical = 14971 ; free virtual = 44741 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:16:37 2019... Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 14973 ; free virtual = 44743 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Loading site data... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 15096 ; free virtual = 44866 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 15123 ; free virtual = 44893 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading route data... Processing options... Creating bitmap... touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2129.430 ; gain = 30.227 ; free physical = 15853 ; free virtual = 45626 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 15816 ; free virtual = 45588 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 15816 ; free virtual = 45588 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15758 ; free virtual = 45530 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15733 ; free virtual = 45505 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15709 ; free virtual = 45482 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15712 ; free virtual = 45485 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15713 ; free virtual = 45485 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15710 ; free virtual = 45483 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15709 ; free virtual = 45481 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Creating bitstream... Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15711 ; free virtual = 45484 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15710 ; free virtual = 45483 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15710 ; free virtual = 45483 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 15744 ; free virtual = 45517 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 2193.262 ; gain = 94.059 ; free physical = 15744 ; free virtual = 45517 Writing placer database... Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 15732 ; free virtual = 45524 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.262 ; gain = 0.000 ; free physical = 15872 ; free virtual = 45672 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 15796 ; free virtual = 45597 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 15781 ; free virtual = 45582 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:16:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2532.227 ; gain = 339.105 ; free physical = 15737 ; free virtual = 45518 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:16:47 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_017/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:10 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 16683 ; free virtual = 46465 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Loading data files... Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1542.863 ; gain = 0.000 ; free physical = 16490 ; free virtual = 46274 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1542.863 ; gain = 0.000 ; free physical = 16488 ; free virtual = 46271 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14814 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2129.766 ; gain = 30.227 ; free physical = 16201 ; free virtual = 45986 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.754 ; gain = 36.215 ; free physical = 16167 ; free virtual = 45951 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.754 ; gain = 36.215 ; free physical = 16167 ; free virtual = 45951 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16120 ; free virtual = 45905 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16101 ; free virtual = 45886 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16101 ; free virtual = 45887 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16101 ; free virtual = 45887 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16101 ; free virtual = 45887 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16101 ; free virtual = 45886 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16101 ; free virtual = 45886 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16097 ; free virtual = 45882 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16096 ; free virtual = 45881 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16096 ; free virtual = 45881 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.809 ; gain = 55.270 ; free physical = 16131 ; free virtual = 45916 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2193.598 ; gain = 94.059 ; free physical = 16130 ; free virtual = 45915 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.434 ; gain = 22.223 ; free physical = 16127 ; free virtual = 45913 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing placer database... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2136.422 ; gain = 28.211 ; free physical = 16085 ; free virtual = 45871 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2136.422 ; gain = 28.211 ; free physical = 16086 ; free virtual = 45873 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16185 ; free virtual = 45977 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16180 ; free virtual = 45973 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16176 ; free virtual = 45970 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16176 ; free virtual = 45970 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16176 ; free virtual = 45970 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16176 ; free virtual = 45970 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16176 ; free virtual = 45970 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16163 ; free virtual = 45958 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16161 ; free virtual = 45957 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16159 ; free virtual = 45954 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 47.266 ; free physical = 16192 ; free virtual = 45987 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2194.266 ; gain = 86.055 ; free physical = 16191 ; free virtual = 45987 Writing placer database... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14892 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.598 ; gain = 0.000 ; free physical = 15994 ; free virtual = 45815 Loading site data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.266 ; gain = 0.000 ; free physical = 15794 ; free virtual = 45606 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Creating bitstream... Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 15547 ; free virtual = 45338 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 15465 ; free virtual = 45256 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 15465 ; free virtual = 45256 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 15509 ; free virtual = 45300 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 15509 ; free virtual = 45300 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 15506 ; free virtual = 45297 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 15501 ; free virtual = 45292 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 15486 ; free virtual = 45278 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 15486 ; free virtual = 45277 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] Phase 1 Build RT Design WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 15498 ; free virtual = 45295 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 15038 Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 15018 ; free virtual = 44817 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 14997 ; free virtual = 44796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14997 ; free virtual = 44796 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14992 ; free virtual = 44791 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:17:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.367 ; gain = 339.105 ; free physical = 14910 ; free virtual = 44708 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:17:14 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_018/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_013 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 15899 ; free virtual = 45698 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 97328c80 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2055.934 ; gain = 91.668 ; free physical = 15832 ; free virtual = 45631 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 97328c80 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 15794 ; free virtual = 45593 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 97328c80 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 15794 ; free virtual = 45593 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1088853dc Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 15745 ; free virtual = 45544 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 15759 ; free virtual = 45558 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 15742 ; free virtual = 45541 Phase 4 Rip-up And Reroute | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 15742 ; free virtual = 45541 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 15742 ; free virtual = 45541 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 15738 ; free virtual = 45537 Phase 6 Post Hold Fix | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 15735 ; free virtual = 45534 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 15716 ; free virtual = 45516 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 15713 ; free virtual = 45513 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 15711 ; free virtual = 45511 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 15741 ; free virtual = 45541 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2109.766 ; gain = 177.516 ; free physical = 15739 ; free virtual = 45538 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 15727 ; free virtual = 45528 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.395 ; gain = 509.531 ; free physical = 15685 ; free virtual = 45484 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2057.930 ; gain = 93.668 ; free physical = 15424 ; free virtual = 45227 --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 15427 ; free virtual = 45230 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 15424 ; free virtual = 45227 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 15424 ; free virtual = 45227 Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6c93b630 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 15369 ; free virtual = 45172 Phase 3 Initial Routing Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 15305 ; free virtual = 45108 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 15283 ; free virtual = 45086 Phase 4 Rip-up And Reroute | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 15282 ; free virtual = 45085 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 15282 ; free virtual = 45085 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 15282 ; free virtual = 45085 Phase 6 Post Hold Fix | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 15281 ; free virtual = 45085 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 15225 ; free virtual = 45028 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 15222 ; free virtual = 45025 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 15219 ; free virtual = 45023 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 15248 ; free virtual = 45052 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2111.762 ; gain = 179.516 ; free physical = 15247 ; free virtual = 45050 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2111.762 ; gain = 0.000 ; free physical = 15182 ; free virtual = 44987 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 15048 ; free virtual = 44853 Loading route data... Processing options... --------------------------------------------------------------------------------- Creating bitmap... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 15098 ; free virtual = 44903 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 509.531 ; free physical = 15169 ; free virtual = 44975 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 15188 ; free virtual = 44993 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 509.531 ; free physical = 15259 ; free virtual = 45065 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15260 ; free virtual = 45067 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 15274 ; free virtual = 45080 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 15274 ; free virtual = 45080 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 15272 ; free virtual = 45078 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1b23f6d9e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 15262 ; free virtual = 45072 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 509.531 ; free physical = 15251 ; free virtual = 45064 Phase 2 Final Placement Cleanup Phase 1 Build RT Design | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.078 ; gain = 50.668 ; free physical = 15226 ; free virtual = 45045 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 509.531 ; free physical = 15164 ; free virtual = 44989 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 2.1 Fix Topology Constraints | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 15166 ; free virtual = 44992 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 15166 ; free virtual = 44992 Creating bitstream... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 509.531 ; free physical = 15122 ; free virtual = 44948 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 15116 ; free virtual = 44943 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 15116 ; free virtual = 44943 Phase 2.2 Pre Route Cleanup Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2.2 Pre Route Cleanup | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 15114 ; free virtual = 44941 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15111 ; free virtual = 44922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 15114 ; free virtual = 44922 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15112 ; free virtual = 44920 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15102 ; free virtual = 44910 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15100 ; free virtual = 44908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15100 ; free virtual = 44908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15099 ; free virtual = 44907 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15099 ; free virtual = 44907 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15095 ; free virtual = 44903 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 15096 ; free virtual = 44904 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1cdf75140 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 15109 ; free virtual = 44916 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 15003 ; free virtual = 44831 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1cdf75140 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14983 ; free virtual = 44811 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14955 ; free virtual = 44783 Phase 4 Rip-up And Reroute | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14941 ; free virtual = 44769 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14929 ; free virtual = 44757 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14916 ; free virtual = 44744 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement Phase 6 Post Hold Fix | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14912 ; free virtual = 44740 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Creating bitstream... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Number of Nodes with overlaps = 0 Phase 7 Route finalize | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14907 ; free virtual = 44730 Phase 8 Verifying routed nets Verification completed successfully --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 14919 ; free virtual = 44728 --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14919 ; free virtual = 44728 --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Phase 8 Verifying routed nets | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14917 ; free virtual = 44726 Phase 9 Depositing Routes Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 14917 ; free virtual = 44726 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14930 ; free virtual = 44739 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4 Rip-up And Reroute | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14943 ; free virtual = 44752 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14953 ; free virtual = 44762 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14949 ; free virtual = 44758 Phase 6 Post Hold Fix | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14937 ; free virtual = 44746 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 9 Depositing Routes | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14947 ; free virtual = 44756 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 14986 ; free virtual = 44795 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:52 . Memory (MB): peak = 2217.781 ; gain = 165.391 ; free physical = 14985 ; free virtual = 44794 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir INFO: [Project 1-570] Preparing netlist for logic optimization 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14978 ; free virtual = 44787 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 14959 ; free virtual = 44768 Phase 9 Depositing Routes Writing placer database... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing bitstream ./design.bit... Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 9 Depositing Routes | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2181.996 ; gain = 97.586 ; free physical = 14878 ; free virtual = 44694 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2181.996 ; gain = 97.586 ; free physical = 14920 ; free virtual = 44736 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 2220.785 ; gain = 168.391 ; free physical = 14918 ; free virtual = 44735 Writing placer database... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 15198 ; free virtual = 45065 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 15121 ; free virtual = 44993 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. output stream error while executing "write_checkpoint -force design.dcp" (procedure "run" line 13) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl" line 19) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:17:32 2019... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_011/OK' failed GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_014 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 16090 ; free virtual = 45911 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 16109 ; free virtual = 45930 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 16102 ; free virtual = 45923 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 16089 ; free virtual = 45910 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 16089 ; free virtual = 45910 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:17:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2531.703 ; gain = 338.105 ; free physical = 16091 ; free virtual = 45911 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:17:33 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1344.074 ; gain = 248.152 ; free physical = 16149 ; free virtual = 45970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_015 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17098 ; free virtual = 46919 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17096 ; free virtual = 46917 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17090 ; free virtual = 46912 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17090 ; free virtual = 46911 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17087 ; free virtual = 46908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17086 ; free virtual = 46907 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17086 ; free virtual = 46907 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 17085 ; free virtual = 46907 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17085 ; free virtual = 46906 INFO: [Project 1-571] Translating synthesized netlist Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:17:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2533.371 ; gain = 339.105 ; free physical = 17001 ; free virtual = 46822 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:17:35 2019... INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- touch build/specimen_019/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1352.105 ; gain = 256.184 ; free physical = 17921 ; free virtual = 47743 --------------------------------------------------------------------------------- Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 6936 #of tags: 6650 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 Creating bitstream... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1352.105 ; gain = 256.184 ; free physical = 17865 ; free virtual = 47688 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17761 ; free virtual = 47585 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.922 ; gain = 324.039 ; free physical = 17949 ; free virtual = 47777 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17948 ; free virtual = 47776 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17957 ; free virtual = 47785 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17940 ; free virtual = 47768 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17935 ; free virtual = 47763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17931 ; free virtual = 47759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17929 ; free virtual = 47757 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17928 ; free virtual = 47756 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.082 ; gain = 264.160 ; free physical = 17927 ; free virtual = 47754 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.090 ; gain = 264.160 ; free physical = 17929 ; free virtual = 47757 INFO: [Project 1-571] Translating synthesized netlist WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Creating bitstream... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 17878 ; free virtual = 47706 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 17857 ; free virtual = 47685 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15572 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:17:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.871 ; gain = 344.105 ; free physical = 17760 ; free virtual = 47589 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:17:43 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 Loading data files... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:17:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2455.867 ; gain = 344.105 ; free physical = 18664 ; free virtual = 48501 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:17:48 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 19333 ; free virtual = 49172 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.953 ; gain = 41.668 ; free physical = 18977 ; free virtual = 48817 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 18935 ; free virtual = 48775 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 18935 ; free virtual = 48774 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 18892 ; free virtual = 48731 INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18932909f Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2087.371 ; gain = 61.086 ; free physical = 18880 ; free virtual = 48720 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 18894 ; free virtual = 48735 --------------------------------------------------------------------------------- Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 520.531 ; free physical = 18892 ; free virtual = 48732 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 520.531 ; free physical = 18886 ; free virtual = 48726 Phase 1.4 Constrain Clocks/Macros Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 18880 ; free virtual = 48721 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 520.531 ; free physical = 18879 ; free virtual = 48720 Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 18879 ; free virtual = 48720 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 18879 ; free virtual = 48719 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 18879 ; free virtual = 48719 Phase 4 Rip-up And Reroute | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 18881 ; free virtual = 48721 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 18881 ; free virtual = 48721 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 18881 ; free virtual = 48721 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 520.531 ; free physical = 18880 ; free virtual = 48720 Phase 2 Final Placement Cleanup INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 6 Post Hold Fix | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 18880 ; free virtual = 48720 Phase 7 Route finalize Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 520.531 ; free physical = 18876 ; free virtual = 48716 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 520.531 ; free physical = 18873 ; free virtual = 48713 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 18873 ; free virtual = 48713 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 18871 ; free virtual = 48711 --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. Phase 7 Route finalize | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 18868 ; free virtual = 48709 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 18862 ; free virtual = 48702 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 18828 ; free virtual = 48668 INFO: [Route 35-16] Router Completed Successfully Processing options... Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 18868 ; free virtual = 48708 Routing Is Done. Creating bitmap... 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.160 ; gain = 135.891 ; free physical = 18863 ; free virtual = 48703 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2130.160 ; gain = 0.000 ; free physical = 18797 ; free virtual = 48642 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15802 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15856 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15916 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 17977 ; free virtual = 47823 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 17946 ; free virtual = 47792 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.441 ; gain = 0.000 ; free physical = 17942 ; free virtual = 47788 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17930 ; free virtual = 47776 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 17874 ; free virtual = 47720 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 17851 ; free virtual = 47697 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 17837 ; free virtual = 47684 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 17836 ; free virtual = 47683 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 17819 ; free virtual = 47666 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 17787 ; free virtual = 47634 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.484 ; gain = 584.562 ; free physical = 17785 ; free virtual = 47632 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17765 ; free virtual = 47612 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17764 ; free virtual = 47611 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17762 ; free virtual = 47609 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17761 ; free virtual = 47608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17761 ; free virtual = 47608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17760 ; free virtual = 47607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17759 ; free virtual = 47606 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17757 ; free virtual = 47604 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 17736 ; free virtual = 47583 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 17626 ; free virtual = 47474 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 17623 ; free virtual = 47472 --------------------------------------------------------------------------------- 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:10 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 17635 ; free virtual = 47484 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16021 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 17796 ; free virtual = 47650 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 17822 ; free virtual = 47676 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 17831 ; free virtual = 47685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 17832 ; free virtual = 47686 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 17834 ; free virtual = 47689 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 17828 ; free virtual = 47682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 17795 ; free virtual = 47649 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 17818 ; free virtual = 47672 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1559.863 ; gain = 0.000 ; free physical = 17752 ; free virtual = 47606 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1559.863 ; gain = 0.000 ; free physical = 17701 ; free virtual = 47555 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 17689 ; free virtual = 47544 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 17594 ; free virtual = 47449 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] Phase 1 Build RT Design | Checksum: e9c56990 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2133.078 ; gain = 48.668 ; free physical = 17456 ; free virtual = 47312 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 17492 ; free virtual = 47348 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading site data... Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 17484 ; free virtual = 47341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 17485 ; free virtual = 47342 --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 17454 ; free virtual = 47310 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: e9c56990 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 17453 ; free virtual = 47309 Phase 2.2 Pre Route Cleanup Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task Phase 2.2 Pre Route Cleanup | Checksum: e9c56990 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 17451 ; free virtual = 47308 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 17443 ; free virtual = 47299 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 17437 ; free virtual = 47293 Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:18:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:39 . Memory (MB): peak = 2607.941 ; gain = 390.160 ; free physical = 17348 ; free virtual = 47205 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:18:11 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 17342 ; free virtual = 47197 Phase 3 Initial Routing ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 16f7d8d1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18025 ; free virtual = 47880 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Bitstream size: 4243411 bytes Phase 4.1 Global Iteration 0 | Checksum: 16f7d8d1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18336 ; free virtual = 48191 Config size: 1060815 words Number of configuration frames: 9996 Phase 4 Rip-up And Reroute | Checksum: 16f7d8d1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18330 ; free virtual = 48186 Phase 5 Delay and Skew Optimization DONE Phase 5 Delay and Skew Optimization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18331 ; free virtual = 48187 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 16f7d8d1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18313 ; free virtual = 48169 Phase 6 Post Hold Fix | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18304 ; free virtual = 48160 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18268 ; free virtual = 48125 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18261 ; free virtual = 48118 Phase 9 Depositing Routes touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Phase 9 Depositing Routes | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18248 ; free virtual = 48106 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 18292 ; free virtual = 48150 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2218.785 ; gain = 166.391 ; free physical = 18288 ; free virtual = 48146 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16151 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 18028 ; free virtual = 47907 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 18017 ; free virtual = 47898 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 18047 ; free virtual = 47929 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 18035 ; free virtual = 47917 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 18013 ; free virtual = 47898 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 17992 ; free virtual = 47878 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17974 ; free virtual = 47862 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.785 ; gain = 0.000 ; free physical = 17970 ; free virtual = 47861 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17949 ; free virtual = 47841 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17948 ; free virtual = 47840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17947 ; free virtual = 47839 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17947 ; free virtual = 47839 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17946 ; free virtual = 47838 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17946 ; free virtual = 47838 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17946 ; free virtual = 47837 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 17945 ; free virtual = 47837 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 17947 ; free virtual = 47838 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.785 ; gain = 0.000 ; free physical = 17936 ; free virtual = 47802 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 17949 ; free virtual = 47815 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17948 ; free virtual = 47814 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17944 ; free virtual = 47810 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17938 ; free virtual = 47804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17942 ; free virtual = 47808 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17941 ; free virtual = 47807 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17940 ; free virtual = 47806 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17941 ; free virtual = 47807 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 17937 ; free virtual = 47803 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 17937 ; free virtual = 47804 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 17914 ; free virtual = 47780 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 17905 ; free virtual = 47772 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 17874 ; free virtual = 47740 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... INFO: [Project 1-570] Preparing netlist for logic optimization Running DRC as a precondition to command write_bitstream No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 17897 ; free virtual = 47764 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 17872 ; free virtual = 47739 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17851 ; free virtual = 47719 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17763 ; free virtual = 47631 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17763 ; free virtual = 47631 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17767 ; free virtual = 47635 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17767 ; free virtual = 47635 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17774 ; free virtual = 47642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17774 ; free virtual = 47642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17775 ; free virtual = 47643 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 17772 ; free virtual = 47639 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 17771 ; free virtual = 47639 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 17887 ; free virtual = 47759 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 17876 ; free virtual = 47747 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 17862 ; free virtual = 47734 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 17792 ; free virtual = 47665 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 17776 ; free virtual = 47648 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7385] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1473.961 ; gain = 0.000 ; free physical = 17689 ; free virtual = 47562 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1473.961 ; gain = 0.000 ; free physical = 17700 ; free virtual = 47574 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 17716 ; free virtual = 47589 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:18:27 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2469.266 ; gain = 339.105 ; free physical = 17715 ; free virtual = 47589 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:18:27 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 17729 ; free virtual = 47603 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 18612 ; free virtual = 48495 --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 18610 ; free virtual = 48485 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18605 ; free virtual = 48480 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 18550 ; free virtual = 48425 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18527 ; free virtual = 48402 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.715 ; gain = 0.000 ; free physical = 18492 ; free virtual = 48367 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1461.715 ; gain = 0.000 ; free physical = 18491 ; free virtual = 48366 touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 18463 ; free virtual = 48340 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18338 ; free virtual = 48215 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18332 ; free virtual = 48209 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18321 ; free virtual = 48198 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18317 ; free virtual = 48194 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18312 ; free virtual = 48189 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18310 ; free virtual = 48187 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18306 ; free virtual = 48183 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18296 ; free virtual = 48173 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 18293 ; free virtual = 48170 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading data files... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 17739 ; free virtual = 47618 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 17616 ; free virtual = 47496 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 17536 ; free virtual = 47417 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 17509 ; free virtual = 47390 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 17504 ; free virtual = 47385 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 17496 ; free virtual = 47377 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 17488 ; free virtual = 47368 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 17482 ; free virtual = 47363 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 17481 ; free virtual = 47362 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 17463 ; free virtual = 47344 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 17487 ; free virtual = 47368 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 17382 ; free virtual = 47265 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 17382 ; free virtual = 47265 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 17306 ; free virtual = 47189 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 17337 ; free virtual = 47220 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17324 ; free virtual = 47207 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2066.172 ; gain = 42.668 ; free physical = 17311 ; free virtual = 47195 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 17277 ; free virtual = 47160 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 17277 ; free virtual = 47160 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16498 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 17246 ; free virtual = 47129 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 17224 ; free virtual = 47108 Phase 1.4 Constrain Clocks/Macros Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 17224 ; free virtual = 47108 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17224 ; free virtual = 47108 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17222 ; free virtual = 47107 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17221 ; free virtual = 47105 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17220 ; free virtual = 47104 --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 17219 ; free virtual = 47104 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17219 ; free virtual = 47103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 17219 ; free virtual = 47103 --------------------------------------------------------------------------------- Phase 5 Delay and Skew Optimization Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17219 ; free virtual = 47103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17218 ; free virtual = 47103 Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 17218 ; free virtual = 47102 --------------------------------------------------------------------------------- Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 17217 ; free virtual = 47101 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 17217 ; free virtual = 47101 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 17217 ; free virtual = 47101 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 17219 ; free virtual = 47103 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Project 1-571] Translating synthesized netlist Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 17177 ; free virtual = 47061 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 17162 ; free virtual = 47046 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 17161 ; free virtual = 47045 Phase 9 Depositing Routes Phase 1 Placer Initialization | Checksum: 208e4f915 Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 17183 ; free virtual = 47067 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 17194 ; free virtual = 47078 Phase 2 Final Placement Cleanup INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 17221 ; free virtual = 47105 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 17221 ; free virtual = 47105 Writing placer database... Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 17212 ; free virtual = 47096 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 17213 ; free virtual = 47100 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 17215 ; free virtual = 47103 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 17214 ; free virtual = 47102 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 15916 ; free virtual = 45809 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 519.531 ; free physical = 15855 ; free virtual = 45748 Phase 1.3 Build Placer Netlist Model 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 15855 ; free virtual = 45747 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 519.531 ; free physical = 15842 ; free virtual = 45735 Phase 1.4 Constrain Clocks/Macros INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 519.531 ; free physical = 15840 ; free virtual = 45734 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 519.531 ; free physical = 15836 ; free virtual = 45729 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.488 ; gain = 519.531 ; free physical = 15840 ; free virtual = 45733 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.488 ; gain = 519.531 ; free physical = 15860 ; free virtual = 45753 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 15857 ; free virtual = 45751 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 15846 ; free virtual = 45740 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 517.531 ; free physical = 15741 ; free virtual = 45636 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 517.531 ; free physical = 15714 ; free virtual = 45608 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 517.531 ; free physical = 15703 ; free virtual = 45598 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 517.531 ; free physical = 15686 ; free virtual = 45581 Phase 2 Final Placement Cleanup report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 517.531 ; free physical = 15669 ; free virtual = 45564 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1485.742 ; gain = 0.000 ; free physical = 15659 ; free virtual = 45554 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1485.742 ; gain = 0.000 ; free physical = 15655 ; free virtual = 45550 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 15655 ; free virtual = 45550 --------------------------------------------------------------------------------- Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 517.531 ; free physical = 15645 ; free virtual = 45541 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 15640 ; free virtual = 45536 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.168 ; gain = 43.668 ; free physical = 15590 ; free virtual = 45485 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.156 ; gain = 48.656 ; free physical = 15524 ; free virtual = 45420 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.156 ; gain = 48.656 ; free physical = 15523 ; free virtual = 45418 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 15429 ; free virtual = 45325 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2083.461 ; gain = 59.961 ; free physical = 15429 ; free virtual = 45325 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 15414 ; free virtual = 45311 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 15412 ; free virtual = 45309 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 15412 ; free virtual = 45308 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 15411 ; free virtual = 45308 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 15411 ; free virtual = 45308 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 15411 ; free virtual = 45307 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 15401 ; free virtual = 45298 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.461 ; gain = 63.961 ; free physical = 15416 ; free virtual = 45313 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.461 ; gain = 63.961 ; free physical = 15439 ; free virtual = 45336 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.461 ; gain = 63.961 ; free physical = 15477 ; free virtual = 45373 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2126.250 ; gain = 134.766 ; free physical = 15478 ; free virtual = 45375 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing placer database... Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2126.250 ; gain = 0.000 ; free physical = 15435 ; free virtual = 45335 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 15400 ; free virtual = 45302 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 15398 ; free virtual = 45297 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 15397 ; free virtual = 45295 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 15396 ; free virtual = 45294 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 15396 ; free virtual = 45294 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 15396 ; free virtual = 45294 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 15394 ; free virtual = 45292 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Creating bitstream... WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 15292 ; free virtual = 45192 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 15271 ; free virtual = 45171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 15271 ; free virtual = 45171 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16771 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 15205 ; free virtual = 45106 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.207 ; gain = 0.000 ; free physical = 14906 ; free virtual = 44814 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... Loading data files... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 14734 ; free virtual = 44643 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 14727 ; free virtual = 44636 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 14733 ; free virtual = 44642 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 14726 ; free virtual = 44635 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 14716 ; free virtual = 44625 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 14717 ; free virtual = 44626 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1931.250 ; gain = 533.562 ; free physical = 14716 ; free virtual = 44625 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:19:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:42 . Memory (MB): peak = 2608.945 ; gain = 390.160 ; free physical = 14564 ; free virtual = 44474 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:01 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 15456 ; free virtual = 45369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 15455 ; free virtual = 45368 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 15406 ; free virtual = 45319 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15418 ; free virtual = 45332 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15660 ; free virtual = 45579 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15655 ; free virtual = 45574 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15653 ; free virtual = 45572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15652 ; free virtual = 45571 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15652 ; free virtual = 45571 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15652 ; free virtual = 45571 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15654 ; free virtual = 45573 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 15652 ; free virtual = 45571 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 15655 ; free virtual = 45574 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 15660 ; free virtual = 45581 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 15641 ; free virtual = 45562 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 15640 ; free virtual = 45562 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 15561 ; free virtual = 45483 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:19:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2470.359 ; gain = 342.105 ; free physical = 15341 ; free virtual = 45264 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:09 2019... Loading site data... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 15994 ; free virtual = 45918 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 508.531 ; free physical = 15920 ; free virtual = 45845 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 508.531 ; free physical = 15905 ; free virtual = 45831 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 508.531 ; free physical = 15902 ; free virtual = 45828 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 508.531 ; free physical = 15899 ; free virtual = 45825 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 508.531 ; free physical = 15893 ; free virtual = 45819 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 508.531 ; free physical = 15892 ; free virtual = 45818 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 15892 ; free virtual = 45817 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 15869 ; free virtual = 45797 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 15798 ; free virtual = 45727 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 15798 ; free virtual = 45726 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 16032 ; free virtual = 45966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 16068 ; free virtual = 46002 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16059 ; free virtual = 45993 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16036 ; free virtual = 45971 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16036 ; free virtual = 45970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16033 ; free virtual = 45967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16033 ; free virtual = 45967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16033 ; free virtual = 45967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16033 ; free virtual = 45967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16033 ; free virtual = 45967 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 16033 ; free virtual = 45967 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 16035 ; free virtual = 45969 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:19:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2461.426 ; gain = 335.176 ; free physical = 16058 ; free virtual = 45993 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:19 2019... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.172 ; gain = 44.668 ; free physical = 17009 ; free virtual = 46944 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. DONE Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.160 ; gain = 49.656 ; free physical = 16967 ; free virtual = 46902 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.160 ; gain = 49.656 ; free physical = 16962 ; free virtual = 46897 touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.465 ; gain = 60.961 ; free physical = 16901 ; free virtual = 46837 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16852 ; free virtual = 46789 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16848 ; free virtual = 46784 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16845 ; free virtual = 46782 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16844 ; free virtual = 46781 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16844 ; free virtual = 46781 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16843 ; free virtual = 46780 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16830 ; free virtual = 46767 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 16828 ; free virtual = 46764 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 16824 ; free virtual = 46761 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 16862 ; free virtual = 46799 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2127.254 ; gain = 136.766 ; free physical = 16862 ; free virtual = 46799 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 16888 ; free virtual = 46829 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 16609 ; free virtual = 46550 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17272 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 16505 ; free virtual = 46446 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 16507 ; free virtual = 46450 Loading data files... Phase 1 Build RT Design | Checksum: 118b3be9c Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2133.078 ; gain = 48.668 ; free physical = 16483 ; free virtual = 46426 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 118b3be9c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 16358 ; free virtual = 46300 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 118b3be9c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 16375 ; free virtual = 46318 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16287 ; free virtual = 46230 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 145a2d7e1 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16256 ; free virtual = 46200 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16256 ; free virtual = 46200 Phase 4 Rip-up And Reroute | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16256 ; free virtual = 46200 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16246 ; free virtual = 46190 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16246 ; free virtual = 46189 Phase 6 Post Hold Fix | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16245 ; free virtual = 46188 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16239 ; free virtual = 46184 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16239 ; free virtual = 46183 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16226 ; free virtual = 46170 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 16269 ; free virtual = 46214 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:52 . Memory (MB): peak = 2216.785 ; gain = 164.391 ; free physical = 16269 ; free virtual = 46214 Writing placer database... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top 0 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:33 2019... ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_015/OK' failed GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_018/OK' failed INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:33 2019... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.227 ; gain = 0.000 ; free physical = 17048 ; free virtual = 46992 ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_014/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' Makefile:54: recipe for target 'clb_int/build/segbits_tilegrid.tdb' failed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2066.176 ; gain = 42.668 ; free physical = 17045 ; free virtual = 46991 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 17010 ; free virtual = 46955 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 17010 ; free virtual = 46955 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 17005 ; free virtual = 46950 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 16995 ; free virtual = 46940 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 16994 ; free virtual = 46939 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 16994 ; free virtual = 46939 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 16994 ; free virtual = 46938 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 16997 ; free virtual = 46942 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.270 ; gain = 576.562 ; free physical = 16997 ; free virtual = 46942 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.172 ; gain = 44.668 ; free physical = 16986 ; free virtual = 46931 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 16949 ; free virtual = 46894 Phase 2.2 Pre Route Cleanup Number of Nodes with overlaps = 0 Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 16946 ; free virtual = 46891 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2083.469 ; gain = 59.961 ; free physical = 16945 ; free virtual = 46890 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 16940 ; free virtual = 46885 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16929 ; free virtual = 46875 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16933 ; free virtual = 46878 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16933 ; free virtual = 46878 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16932 ; free virtual = 46878 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16932 ; free virtual = 46877 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16927 ; free virtual = 46873 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 16911 ; free virtual = 46856 Phase 8 Verifying routed nets Number of Nodes with overlaps = 0 Verification completed successfully Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 16908 ; free virtual = 46854 Phase 3 Initial Routing Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 16909 ; free virtual = 46854 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 16905 ; free virtual = 46850 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 16943 ; free virtual = 46888 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 16943 ; free virtual = 46888 Writing placer database... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16931 ; free virtual = 46876 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16924 ; free virtual = 46870 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16923 ; free virtual = 46869 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16923 ; free virtual = 46869 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16921 ; free virtual = 46867 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16922 ; free virtual = 46867 Phase 1 Build RT Design | Checksum: 1307d6b8e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2057.930 ; gain = 93.668 ; free physical = 16922 ; free virtual = 46868 Phase 7 Route finalize Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1307d6b8e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 16885 ; free virtual = 46831 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1307d6b8e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 16885 ; free virtual = 46831 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 16875 ; free virtual = 46822 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 16878 ; free virtual = 46825 Phase 9 Depositing Routes Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 16864 ; free virtual = 46813 Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 16860 ; free virtual = 46809 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 16897 ; free virtual = 46846 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2128.254 ; gain = 137.766 ; free physical = 16898 ; free virtual = 46847 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6d37d05e Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16883 ; free virtual = 46829 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 16834 ; free virtual = 46784 Starting Routing Task Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d37d05e Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16815 ; free virtual = 46765 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16800 ; free virtual = 46751 Phase 4 Rip-up And Reroute | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16800 ; free virtual = 46750 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16799 ; free virtual = 46750 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16798 ; free virtual = 46749 Phase 6 Post Hold Fix | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 16798 ; free virtual = 46748 Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 7 Route finalize Phase 1 Build RT Design INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 16837 ; free virtual = 46784 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 16835 ; free virtual = 46783 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 16836 ; free virtual = 46784 Loading site data... INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 16865 ; free virtual = 46813 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 16864 ; free virtual = 46812 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 16850 ; free virtual = 46798 --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 16865 ; free virtual = 46815 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 16864 ; free virtual = 46813 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 16860 ; free virtual = 46809 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Device 21-403] Loading part xc7z020clg400-1 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 16811 ; free virtual = 46759 --------------------------------------------------------------------------------- Loading route data... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 133887d51 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2057.934 ; gain = 94.668 ; free physical = 16192 ; free virtual = 46148 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17477 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2063.922 ; gain = 100.656 ; free physical = 16198 ; free virtual = 46154 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2063.922 ; gain = 100.656 ; free physical = 16199 ; free virtual = 46154 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 106.711 ; free physical = 16280 ; free virtual = 46236 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 106.711 ; free physical = 16185 ; free virtual = 46142 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 106.711 ; free physical = 16167 ; free virtual = 46124 Phase 4 Rip-up And Reroute | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 106.711 ; free physical = 16167 ; free virtual = 46123 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 106.711 ; free physical = 16166 ; free virtual = 46123 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 106.711 ; free physical = 16166 ; free virtual = 46123 Phase 6 Post Hold Fix | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 106.711 ; free physical = 16165 ; free virtual = 46122 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 16137 ; free virtual = 46094 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2072.977 ; gain = 109.711 ; free physical = 16134 ; free virtual = 46091 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2072.977 ; gain = 109.711 ; free physical = 16133 ; free virtual = 46089 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2072.977 ; gain = 109.711 ; free physical = 16163 ; free virtual = 46120 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2111.766 ; gain = 180.516 ; free physical = 16161 ; free virtual = 46118 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 16088 ; free virtual = 46045 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 15882 ; free virtual = 45839 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 15871 ; free virtual = 45829 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Command: report_drc (run_mandatory_drcs) for: bitstream_checks --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15867 ; free virtual = 45825 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 15867 ; free virtual = 45825 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15826 ; free virtual = 45783 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15824 ; free virtual = 45781 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15815 ; free virtual = 45773 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15813 ; free virtual = 45771 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15810 ; free virtual = 45768 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 15809 ; free virtual = 45767 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 15809 ; free virtual = 45767 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:19:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2462.430 ; gain = 335.176 ; free physical = 15792 ; free virtual = 45751 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:46 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15798 ; free virtual = 45756 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15801 ; free virtual = 45759 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15802 ; free virtual = 45760 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15804 ; free virtual = 45762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15803 ; free virtual = 45761 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15803 ; free virtual = 45761 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15805 ; free virtual = 45763 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 15818 ; free virtual = 45776 Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 15817 ; free virtual = 45775 INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 16304 ; free virtual = 46265 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 16173 ; free virtual = 46134 --------------------------------------------------------------------------------- Loading site data... Loading site data... Phase 1 Build RT Design | Checksum: 1412f7e16 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 16088 ; free virtual = 46049 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1412f7e16 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 16047 ; free virtual = 46008 Phase 2.2 Pre Route Cleanup Starting Placer Task Phase 2.2 Pre Route Cleanup | Checksum: 1412f7e16 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 16045 ; free virtual = 46007 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 16037 ; free virtual = 45999 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 16037 ; free virtual = 45999 Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2086.250 ; gain = 59.961 ; free physical = 15964 ; free virtual = 45926 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] Number of Nodes with overlaps = 0 WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] Phase 3 Initial Routing | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 15946 ; free virtual = 45908 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 15946 ; free virtual = 45908 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] Phase 4 Rip-up And Reroute | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 15952 ; free virtual = 45914 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 15947 ; free virtual = 45909 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 15950 ; free virtual = 45912 Phase 6 Post Hold Fix | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 15952 ; free virtual = 45914 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 15984 ; free virtual = 45947 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 15983 ; free virtual = 45946 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 15984 ; free virtual = 45947 Phase 9 Depositing Routes Creating bitstream... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 15991 ; free virtual = 45954 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 15992 ; free virtual = 45956 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 15992 ; free virtual = 45956 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 16030 ; free virtual = 45993 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 2130.039 ; gain = 135.766 ; free physical = 16030 ; free virtual = 45993 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 16027 ; free virtual = 45990 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.90 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2130.039 ; gain = 0.000 ; free physical = 15966 ; free virtual = 45933 Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 37 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 2455.867 ; gain = 345.105 ; free physical = 16599 ; free virtual = 46575 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:57 2019... Loading site data... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. touch build/specimen_014/OK Loading data files... Creating bitstream... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:19:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 2471.359 ; gain = 343.105 ; free physical = 17373 ; free virtual = 47350 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:58 2019... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 17394 ; free virtual = 47371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 17423 ; free virtual = 47400 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 17436 ; free virtual = 47413 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 1077248 bytes ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_014/OK' failed INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:19:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2463.434 ; gain = 336.176 ; free physical = 18315 ; free virtual = 48292 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:19:59 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18326 ; free virtual = 48303 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18321 ; free virtual = 48298 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18317 ; free virtual = 48294 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18317 ; free virtual = 48294 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18317 ; free virtual = 48294 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18317 ; free virtual = 48294 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18317 ; free virtual = 48294 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 18320 ; free virtual = 48297 Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.676 ; gain = 216.219 ; free physical = 18322 ; free virtual = 48300 INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes Config size: 1060815 words Writing bitstream ./design.bit... Number of configuration frames: 9996 DONE ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_015/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' Makefile:87: recipe for target 'dsp/build/segbits_tilegrid.tdb' failed INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization 37 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2453.871 ; gain = 342.105 ; free physical = 19572 ; free virtual = 49550 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:20:00 2019... Bitstream size: 262144 bytes ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_015/OK' failed INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1398.668 ; gain = 315.773 ; free physical = 20455 ; free virtual = 50434 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.699 ; gain = 0.000 ; free physical = 20331 ; free virtual = 50311 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1462.699 ; gain = 0.000 ; free physical = 20330 ; free virtual = 50311 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 20070 ; free virtual = 50051 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 20060 ; free virtual = 50042 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 20060 ; free virtual = 50041 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 20060 ; free virtual = 50041 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 20060 ; free virtual = 50041 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 20060 ; free virtual = 50041 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 20061 ; free virtual = 50043 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 20061 ; free virtual = 50043 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 15af38611 Time (s): cpu = 00:00:33 ; elapsed = 00:00:31 . Memory (MB): peak = 2066.953 ; gain = 41.668 ; free physical = 20014 ; free virtual = 49996 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15af38611 Time (s): cpu = 00:00:33 ; elapsed = 00:00:31 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 19982 ; free virtual = 49964 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15af38611 Time (s): cpu = 00:00:33 ; elapsed = 00:00:31 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 19981 ; free virtual = 49964 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10d853c8e Time (s): cpu = 00:00:34 ; elapsed = 00:00:31 . Memory (MB): peak = 2087.371 ; gain = 62.086 ; free physical = 19960 ; free virtual = 49943 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10d853c8e Time (s): cpu = 00:00:34 ; elapsed = 00:00:31 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 19961 ; free virtual = 49943 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 19960 ; free virtual = 49943 Phase 4 Rip-up And Reroute | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 19960 ; free virtual = 49943 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 19960 ; free virtual = 49943 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 19960 ; free virtual = 49943 Phase 6 Post Hold Fix | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 19960 ; free virtual = 49943 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 19958 ; free virtual = 49941 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 19958 ; free virtual = 49941 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10d853c8e Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 19957 ; free virtual = 49940 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 19996 ; free virtual = 49979 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2130.160 ; gain = 136.891 ; free physical = 19995 ; free virtual = 49978 Writing placer database... INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:20:08 2019... Creating bitstream... ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_013/OK' failed Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 42 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:32 ; elapsed = 00:00:17 . Memory (MB): peak = 2468.145 ; gain = 338.105 ; free physical = 21190 ; free virtual = 51175 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:20:10 2019... Bitstream size: 569344 bytes ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_012/OK' failed Phase 1 Build RT Design | Checksum: 13f8005f1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 22043 ; free virtual = 52030 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13f8005f1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 22008 ; free virtual = 51995 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13f8005f1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 22008 ; free virtual = 51995 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12bd49b1d Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 21967 ; free virtual = 51954 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21959 ; free virtual = 51946 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21959 ; free virtual = 51945 Phase 4 Rip-up And Reroute | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21958 ; free virtual = 51945 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21957 ; free virtual = 51944 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21956 ; free virtual = 51943 Phase 6 Post Hold Fix | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21954 ; free virtual = 51941 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21944 ; free virtual = 51931 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2094.250 ; gain = 67.961 ; free physical = 21937 ; free virtual = 51923 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12bd49b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2094.250 ; gain = 67.961 ; free physical = 21878 ; free virtual = 51865 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2094.250 ; gain = 67.961 ; free physical = 21910 ; free virtual = 51897 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 2133.039 ; gain = 138.766 ; free physical = 21907 ; free virtual = 51893 Writing placer database... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.188 ; gain = 0.000 ; free physical = 21793 ; free virtual = 51780 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:20:14 2019... ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_014/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' Makefile:84: recipe for target 'bram_int/build/segbits_tilegrid.tdb' failed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1932.230 ; gain = 469.531 ; free physical = 22748 ; free virtual = 52735 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1932.230 ; gain = 469.531 ; free physical = 22748 ; free virtual = 52735 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1932.230 ; gain = 469.531 ; free physical = 22748 ; free virtual = 52735 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1932.230 ; gain = 469.531 ; free physical = 22748 ; free virtual = 52735 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1932.230 ; gain = 469.531 ; free physical = 22748 ; free virtual = 52735 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1932.230 ; gain = 469.531 ; free physical = 22749 ; free virtual = 52736 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1932.230 ; gain = 533.562 ; free physical = 22749 ; free virtual = 52736 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 972cf7e0 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 22607 ; free virtual = 52599 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 972cf7e0 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 22575 ; free virtual = 52567 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 972cf7e0 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 22575 ; free virtual = 52567 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 155c195dd Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22572 ; free virtual = 52565 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22569 ; free virtual = 52561 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22569 ; free virtual = 52561 Phase 4 Rip-up And Reroute | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22569 ; free virtual = 52561 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22569 ; free virtual = 52561 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22569 ; free virtual = 52561 Phase 6 Post Hold Fix | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22569 ; free virtual = 52561 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22569 ; free virtual = 52561 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 22567 ; free virtual = 52559 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 155c195dd Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 22567 ; free virtual = 52559 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 22601 ; free virtual = 52593 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 22601 ; free virtual = 52593 Writing placer database... Writing XDEF routing. output stream error while executing "write_checkpoint -force design.dcp" (procedure "generate_top" line 13) invoked from within "generate_top" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl" line 3) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:20:26 2019... ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_016/OK' failed Phase 1 Build RT Design | Checksum: 15b0a291a Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2058.914 ; gain = 94.668 ; free physical = 23541 ; free virtual = 53537 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15b0a291a Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2064.902 ; gain = 100.656 ; free physical = 23510 ; free virtual = 53507 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15b0a291a Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2064.902 ; gain = 100.656 ; free physical = 23510 ; free virtual = 53507 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2070.957 ; gain = 106.711 ; free physical = 23506 ; free virtual = 53502 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2071.957 ; gain = 107.711 ; free physical = 23503 ; free virtual = 53500 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2071.957 ; gain = 107.711 ; free physical = 23503 ; free virtual = 53500 Phase 4 Rip-up And Reroute | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2071.957 ; gain = 107.711 ; free physical = 23503 ; free virtual = 53500 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2071.957 ; gain = 107.711 ; free physical = 23503 ; free virtual = 53500 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2071.957 ; gain = 107.711 ; free physical = 23503 ; free virtual = 53500 Phase 6 Post Hold Fix | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2071.957 ; gain = 107.711 ; free physical = 23503 ; free virtual = 53500 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2071.957 ; gain = 107.711 ; free physical = 23503 ; free virtual = 53500 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2074.957 ; gain = 110.711 ; free physical = 23501 ; free virtual = 53498 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 115f91288 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2074.957 ; gain = 110.711 ; free physical = 23502 ; free virtual = 53499 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2074.957 ; gain = 110.711 ; free physical = 23535 ; free virtual = 53532 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2113.746 ; gain = 181.516 ; free physical = 23535 ; free virtual = 53532 Writing placer database... Writing XDEF routing. output stream error while executing "write_checkpoint -force design.dcp" (procedure "generate_top" line 13) invoked from within "generate_top" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl" line 3) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:20:35 2019... ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_017/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' Makefile:93: recipe for target 'fifo_int/build/segbits_tilegrid.tdb' failed make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' Makefile:116: recipe for target 'run' failed make[1]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid'